Principles of CCPPrinciples of CCP - Microchip …

1 Principles of CCP. CCP module Implementation and Functionality Created by: Date: Welcome to Getting Started module on Capture, Compare and Pulse Width Modulation feature, abbreviated CCP. The CCP module will discuss initialization and function of on-board CCP resources 1. Principles of CCP. l CCP Modules Capability l Capture - The contents of the 16 bit timer, upon detecting an n th rising or falling edge, is written to internal registers l Compare - Generate an interrupt, or change on output pin, when Timer 1 matches a pre-set comparison value l PWM - Create a re-configurable steady duty cycle square wave output at a user set frequency Created by: Date: A capture, compare, and PWM, module , or CCP for short, is designed into the PicMicro to assist with measurement or control of time based pulse signals.

2 Capture mode causes the contents of an internal 16 bit timer, upon detecting an n th rising or falling edge, to be written to on-board special function registers Compare mode generates an interrupt, or change on output pin, when Timer 1. matches a pre-set comparison value PWM, or formally pulse width modulation, mode creates a re-configurable square wave duty cycle output at a user set frequency. The application software can change the duty cycle or period by modifying the value written to specific special function register. Future slides in the Principles of CCP module describes how the different modes are set and operate. Note, the CCP module integrates with Timer one and two to perform operation. Therefore, a review Timer slide may be helpful after viewing the CCP module .

3 2. Principles of CCP. l CCP Resource Summary l Single source clocks for Capture and Compare or PWM modes l Two separate CCP Modules l Each CCP module supports Capture, Compare or PWM modes Created by: Date: The mid-range Pic micro-controller can contain up to two CCP modules. Each module operates independently, and supports capture, compare or PWM mode. Operation is synchronized to internal clocks. A single clock source is shared between all available Capture and Compare or PWM CCP modules on chip. A CCP module 's mode is determined by the designer's specified options in the CCPxCON register, where x' will be 1' or 2' . We will begin with examining CCPxCON configurations, and will continue to the initialization, operation and design notes for each of the CCP modes.

4 When starting into any new design and chip selection, please check the Microchip web site( ) for errata sheets discussing known deviations from the original datasheet. 3. Principles of CCP. l CCP Register nomenclature l CCPxCON == CCP1 CON or CCP2 CON. l CCPxSTAT == CCP1 STAT or CCP2 STAT. l CCPxL == CCP1L or CCP2L. l CCPxH == CCP1H or CCP2H. Created by: Date: A quick overview on nomenclature used in the CCP module and other documents supplied by Microchip . As a general rule, if the part contains two or more modules with duplicate functionality and special function registers, like TXREG1 and TXREG2, the use of an index variable x' with be used in documentation to refer to module 1 or module 2 register.

5 To re-examine our TXREG1 and TXREG2 example, the data sheet will commonly refer to TXREGx as either TXREG1 or TXREG2. Other examples centered toward CCP dual module documentation: CCPxCON - refers to CCP one or CCP two control register, supporting the mode selection and access to the two least significant CCPxL - refers to CCP one or CCP two is used to store low byte value in Capture or compare operation and as entry register in PWM mode. CCPxH - refers to CCP one or CCP two used to store high Byte value in capture or compare mode and as buffer in PWM mode. 4. Principles of CCP. l CCPxCON Configuration Setup CCPxCON<7:6> == 00'b CCPxCON<5:4> == DCB1:DCBxB0. CCPxCON<3:0> == CCPxM3:CCPxM0. l CCP Mode Configuration Chart- Capture Tim e r CCPxM3: TRIS Mode F la g Activity source M0 S e tting Change Tim e r 1 0000'b 1(input) C a p ture ------- P W M O ff ( re s e t C C P x m o d u le ).

6 Tim e r 1 0100'b 1(input) C a p ture ------- Te s t every fa llin g e d g e Tim e r 1 0101'b 1(input) C a p ture ------- Te s t every ris in g e d g e Tim e r 1 0110'b 1(input) C a p ture ------- Te s t every 4th ris in g e d g e Tim e r 1 0111'b 1(input) C a p ture ------- Te s t every 16th ris in g e d g e Created by: Date: Each CCPxCON register contains mode control bits(CCPxM3:CCPxM0) and the two least significant bits of the PWM pulse. For all cases, CCPxCON bit 7 and 6 are unused and zero is written to these locations when doing a byte write to CCPxCON. CCPxCON bits 5 and 4 are least significant bits for PWM mode, and are don't care in capture or compare mode. By writing to bits CCPxM3:CCPxM0, a designer can select the desired mode of operation.

7 A more detailed explanation for each of modes is discussed later in the CCP training module 5. CCP - Capture Mode l Initialization of CCP Capture Mode l Set the TRIS bit for input to support CCPx pin operation l Signal transition at the input pin is sampled for the 1st, 4th, 16th rising edge or the first falling edge recorded causes a capture event l Timer 1 must be turned on to have a continuous clock source Created by: Date: Before using the CCP module for operation, initialization of CCPx pin data direction, selection of CCP mode, and timer 1 or timer 2 setup and is required. When configuring for capture mode, the TRIS bit, corresponding to the CCPx pin, must be SET to support detection of incoming pulses.

8 Capture mode is selected when CCPxM3:CCPxM2 =b' 01, and the number of required rising edges, divided by 1,4 or 16, or a single falling edge required before the capture event will trigger can be set from CCPxM1:CCPxM0. Since capture mode depends on Timer one as its reference clock, timer one must be enabled and configured for continuous clock source. 6. CCP - Capture Mode l Conceptual View - Capture Mode Operation Capture Mode Functional Diagram: TMR H &. CCPxIF L Register CCPx Pin Prescale 1, 4 or 16 Transfer TMR. and edge detect CCPRxH CCPRxL. Created by: Date: The capture mode functional diagram illustates how the incoming pulses are divided by the pre-scaler value before setting the CCPxIF flag, indicating a positive capture condition/event.

9 The signal evaluated by the pre-scaler originates from the external CCPx pin and routed to the pre-scale circuitry. A pre-scaler is used to increase the number of edge counts required before sending the CCPxIF and transferring Timer high and low contents to CCPRxH and CCPRxL registers. 7. CCP - Capture Mode l Operation of CCP Capture Mode l Following the occurrence of a capture event 1. Interrupt flag bit(CCPxIF) is set, requiring an exercise of software to clear the flag bit 1 contents is recorded in the CCPRxH and CCPRxL(high and low bytes). l CCPRxH and CCPRxL are only single level buffered, requiring capture data is read before the next consecutive capture event Created by: Date: Following the occurrence of a capture event, CCPx module generates two actions: Initially, timer 1 contents, high and low byte, is recorded in CCPRxH, high byte, and CCPRxL, low byte.

10 Secondly, the interrupt flag bit, CCPxIF, is set. If CCPxIF is set and CCPxIE is enabled, the main code execution is paused and the interrupt handler is called. The interrupt handler must clear CCPxIF bit to allow detection of the next capture event condition. Independent of the capture register pre-scaler, CCPRxH and CCPRxL are only single level buffered, requiring the CCPRx register data be saved to another register set before the next consecutive capture event. 8. CCP - Capture Mode l Design Notes - Capture Mode l Changing from one capture pre-scale to another may generate an interrupt, and the pre-scalar counter may not be cleared l When a mid-range PIC is placed in SLEEP. and CCP interrput is enabled, Timer 1 pre- scaler will continue to count, and will only wake up from sleep if triggered by an event NOTE: Timer 1 value is not read into CCPxH.