Random Offset in CMOS IC Design - Designer’s Guide

1 Random Offset in cmos IC DesignECEN4827/5827 analog IC DesignOctober 19, 2007 Art Zirger, National to start? How do we choose what transistor sizes to use in a Design ? One topic not often discussed in classes is Random offsetand how transistor sizing affects this 2 devices (MOSFET s, resistors, capacitors) of the same size, laid out next to each other, are not identical. How they differ is generally the function of Random offsets during processing. These offsets vary from chip to chip and set a limit on precision attainable which is typically reflected as data sheet Definitions/Notation The following I-V equation for a MOSFET in saturation is used:where A mixture of Vt& VTis used where both are referring to threshold voltage, not thermal voltage()22tGSDVVI = LWCox =AgendaSystematic vs. Random offsetSources & profiles of Random offsetCurrent Mirror/Diff Pair Offset derivation & insightsPropagation of uncertainties mathCurrent Mirror/Diff Pair exercisesSystematic vs.

2 Random mismatch Systematic Mismatch in the circuit (or layout) because of poor designer choices ( avoidable) Each copy of the circuit should share this; calculable based on the average values of element parameters Viewable using SPICE DC operating point simulation Random Mismatch in the circuit because of wafer processing Different chips will have different values, but the value will mostly remain the same (subject to temperature shifts, drift, etc.) Each copy of the circuit should share this; calculable based on the statistical values of element parameters Viewable using DCmatch and Monte Carlo simulations This is what is usually thought of as matchingSources of Random mismatch Sources of Random mismatch include: Edge effects (rough edges) Implantation (finite number of charges & distribution) Mobility Oxide effectsSee References (after Summary slide) for more parameters Commonly investigated mismatch parameters: MOSFETVt, (mobility and W/L), (Body Effect) Resistors (resistivity) Capacitorsoxide thickness variation This presentation covers Vt& mismatchProfile of Random mismatch Has a gaussian distribution Can be quantified by statistical variables of: mean: standard deviation: a variance: 2a Mismatch is defined as occurring between elements.

3 A single element does not have mismatch, but a self mismatch can be Voltage MismatchThe threshold voltages among a group of transistors has a gaussian profile about a mean. Experimentally, it has been shown that the difference in threshold voltages between 2 identically sized transistorsbehaves as:Note that to reduce the mismatch by takes 4 times the fab will create test structures and measure Vtmultiple times per wafer for various sizes of transistors and collect ongoing statistics to monitor the process over Threshold Voltage Mismatch, cont dFrom W. Sansen showing how the mismatch constant, AVT, varies roughly linearly with process size (doping concentration affects linearity of the relationship). Also, for p substrates, the PMOS will have AVT~ * cmos AVTNFETC urrent Factor MismatchCurrent Factor, , behaves fractionally, as:A ~ 2% m, invariant of processNational Semiconductor does not have this value characterized, so we may use this approximate value to estimate whether we need to worry about this or not.

4 ()WLA = Offset Derivation Given the behavior of sufficiently uncorrelated parameters, want to know the effect of those parameters on 2 common circuits: Current mirror Differential pair Start with I-V equation for MOSFET and apply total differential :..+ + + = zzfyyfxxffOffset Derivation Current MirrorWhat is the fractional error in the currents being mirrored in a 1:1 current mirror?()22 TgsDVVI = TgsVV,, variablesDmIg 2=TgsDVVI 2or()()()TgsgsTgsTTgsDVVVVVVVVI + = 2222212 ()()()()222222221 TgsTgsTTgsTgsDDVVVVVVVVVII = ()TgsTDDVVVII = 2 Vgs= 0 in a current by IDto get fractional error:TDmDDVIgII = Offset Derivation Diff PairWhat is VGSfor 2 transistors operating at the same current?()22 TgsDVVI = TgsVV,, DmIg 2=TgsDVVI 2or()()()TgsgsTgsTTgsDVVVVVVVVI + = 2222212 0= DI()()gsTTgsTgsVVVVVV + =222102 Constant current so Divide by ()TgsVV 22 ()TTgsgsVVVV + = 2 TmDgsVgIV + = Offset Derivation Summary/Insights Differential Pairs and Current Mirrors operate with very different gm/Id( bias point) ratios to minimize mismatch errors: Differential Pair:High gm/Id low overdrive Current Mirror:Low gm/Id high overdrive You can achieve this by designing differential pairs with large W/Land current mirrors with small W/LratiosTmDgsVgIV + = TDmDDVIgII = Offset Derivation w/Standard Deviations Given the expected functional relationships of the 2 different Offset behaviors, for various statistical reasons, you express these relationships in terms of standard deviations as.

5 Current MirrorDifferential PairTDmDDVIgII = TmDgsVgIV + = ()()()()22 TmDgsVgIV + = ()()()22 + = TDmDDVIgII Statistics Math You need to know how to propagate uncertainties to get the most out of this material. General form to propagate uncertainties for uncorrelated variables:z = f(x,y, )( n = # of variables ) = =nivizivf1222 ..222+ + =yxzyfxf Statistics Math, cont d More commonly seen as this: Sum: , (square) root sum of squares Product/Quotient: f(x,y) = x*y or x/yFractional error of f is the of the fractional errors of the +=22 + =yxfyxf Statistics Math, cont dTo utilize these error propagation formulas, you need to know the individual contributions ( x, y) which means you need the self-mismatch of the variables in question. This is found by noting that, if:and we apply the sum formula, we get:or With a self-mismatch defined, we can now calculate the standard deviation of all sorts of mathematical operations of statistical parameters.

6 We can calculate the accuracy of a 50x current mirror, for example, by utilizing the quotient version to propagate the uncertainty of the mirror gain. WLAtttttVVVVV==+= 222221 WLAttVV22,1= 21tttVVV = Statistics Math - Summary To propagate a ..sum: z = x + yproduct: z = x*y quotient: z = x/y222yxz +=() + =2222yxxyyxz ()()222yxzxy +=2222 + =yxyyxz + =2222yxyxyxz Current Mirror Matching Example Ratios: 1:1:1:50 Problem: Design 1:1 to required accuracy (1%), for Id=1 A Procedure: Calculate self-mismatch and utilize 1x 1x 50x PMOS: pCox=23 A/ m, Id= 1 A If mismatch not modeled, Design 1:1 mirrors for 1%: & Note: no dependence on W, only L!!Use W/L=2u/16uCurrent Mirror Matching, cont d()()()22 + = TDmDDVIgII ()()TDmDDVIgII = LWICII gdoxpddm 22==()AALmVICLAWLALWICII doxpVVdoxpdselfdtt 1232322=== () () dselfdII WLAttVV22,1= =LLCurrent Mirror Circuit 1:1:1 all have TDW = 2u 50x has TDW = 2u*50 = 100u1x 1x 1x 50xCurrent Mirror Followup Did neglecting mismatch matter?

7 What is the matching for the 50x mirror?See Appendix BDiff Pair ExampleUse analysis to estimate input Offset voltage to diff Vgsof input d/Idof current mirror and reflect to input using gmof input 2 independent sources using sum propagationDiff Pair Circuit, Quiescent ConditionsNeed to know things like gm, Idfor total Offset calculationsDiff Pair Circuit, Step 11. Calculate Vgsof input pair W/L = 20u/.5u, AVt= 16mV m gm_M0/M1= A/V, Id= A, ~ 2% m Total = *2016=== ()()()()22 TmDgsVgIV + = () * * ()()( ) += Diff Pair Circuit, Step 21. Calculate Id/Idof mirror pair Reflect current error to input Offset through gmN()()() * * + = + = mmmmVAVAmmmVIgIITDmDD () * *== = Diff Pair, Step 3 ( ) Last step is to combine these 2 independent sources of error into the total: input pair current mirror Given a choice to add area to current mirrors or input pair, in this example, more to be gained by using the area for the input pair.

8 ()() += Summary Points Current mirror accuracy is improved with low W/L ratios If mismatch is not a factor, current mirror accuracy is determinedby selection of L only. Differential pair accuracy is improved with high W/L ratios Based on surveys of published fabrication data, you can estimate mismatch coefficients for your own process rather easily Uncorrelated statistics provide the basis to propagate individual mismatch information to arbitrary destinations Random mismatch can be improved with more area but it s costly: CAD tool analyses such as DCmatch and Monte Carlo are a useful tools for getting insight into sources of mismatch (expected and unexpected)WLmismatch1 References Layout: The Art of analog Layout, Alan Hastings General Information: analog Design Essentials, W. C. Sansen Early classic paper and commentary: Matching properties of MOS transistors, Marcel J.

9 M. Pelgrom, JSSC, Oct. 1989 Recent papers with references: Device mismatch and tradeoffs in the Design of analog circuits , Peter Kinget, JSSC, June 2005 (in depth, with many references) Device Mismatch: An analog Design Perspective , Peter Kinget, ISCAS 2007, (condensed information) Cadence application note on DCmatch: Affirma Spectre DC Device Matching Analysis TutorialAppendix A CAD tools Cadence and other vendors have analyses to assist in propagating mismatch sensitivities to designated voltage nodes or current branches 2 analyses which we use are: DCMatch Monte CarloTools for Checking Matching Local mismatch: DCMatch (Spectre analysis) Uses small signal analysis to reflect the combination of modeled mismatches to an arbitrary output node By local , we mean the signal deviations introduced must not alter the dc operating point for the results to be accurate ( small signal assumption) Fast to runTools for Checking Matching Global mismatch: Monte Carlo Alters parameters of individual elements, drawing variation from a statistical distribution.

10 Pro: Unlike DCMatch, doesn t rely on linear approximation, so does a (slightly) better estimate of matching, because real components are nonlinear. Con: You need to run 100 s of simulations to develop good statistics which means this takes 100 s of times longer than DCMatch (which is 1 DC simulation); reported mean should be close to DC simulation if enough points are for Checking Matching1. Use hand calculations to estimate required transistor sizes to meet matching2. Utilize DCMatch to verify hand calculations. In more complicated circuits, a sensitivity from an unexpected transistor can show up3. Later, utilize Monte Carlo to double checkCurrent Mirror Circuit 1:1:1 all have TDW = 2u 50x has TDW = 2u*50 = 100u1x 1x 1x 50xCurrent Matching: DCMatchSelect dcmatch Output is a probe ( current), the voltage source, sensitivities found are from M1 and M0.