SEMICONDUCTOR MEMORIES

1 Digital Integrated Circuits Prentice Hall 1995 MemorySEMICONDUCTORMEMORIESD igital Integrated Circuits Prentice Hall 1995 MemoryChapter Overview Memory Classification Memory Architectures The Memory Core Periphery ReliabilityDigital Integrated Circuits Prentice Hall 1995 MemorySemiconductor MemoryClassificationRWMNVRWMROMEPROME2 PROMFLASHR andomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOS hift RegisterCAMLIFOD igital Integrated Circuits Prentice Hall 1995 MemoryMemory Architecture: DecodersWord 0 Word 1 Word 2 Word N-1 Word N-2 Input-OutputS0S1S2SN-2SN_1(M bits)StorageCellM bitsN WordsWord 0 Word 1 Word 2 Word N-1 Word N-2 Input-Output(M bits)StorageCellM bitsDecoderA0A1AK-1S0N words => N select signalsToo many select signalsDecoder reduces # of select signalsK = log2 NDigital Integrated Circuits Prentice Hall 1995 MemoryArray-Structured Memory ArchitectureInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1 Storage CellSense Amplifiers /.

2 ASPECT RATIO or HEIGHT >> WIDTHA mplify swing torail-to-rail amplitudeSelects appropriatewordDigital Integrated Circuits Prentice Hall 1995 MemoryHierarchical Memory ArchitectureGlobal Data BusRowAddressColumnAddressBlockAddressBl ock SelectorGlobalAmplifier/DriverI/OControl CircuitryAdvantages:1. Shorter wires within blocks2. Block address activates only 1 block => power savingsDigital Integrated Circuits Prentice Hall 1995 MemoryMemory Timing: DefinitionsREADWRITEDATARead AccessRead AccessRead CycleData ValidData WrittenWrite AccessWrite CycleDigital Integrated Circuits Prentice Hall 1995 MemoryMemory Timing: ApproachesAddressBusRASCASRAS-CAS timingAddressBusAddressAddress transitioninitiates memory operation DRAM TimingSRAM TimingRow AddressColumn AddressMSBLSBM ultiplexed AdressingSelf-timedDigital Integrated Circuits Prentice Hall 1995 MemoryMOS NOR ROMWL[0]WL[1]WL[2]WL[3]BL[0]BL[1]BL[2]BL [3]GNDGNDVDDPull-up devicesDigital Integrated Circuits Prentice Hall 1995 MemoryMOS NOR ROM LayoutMetal1 on top of diffusionBasic cell10 x 7 2 WL[0]WL[1]WL[2]WL[3]GND (diffusion)Metal1 PolysiliconOnly 1 layer (contact mask)

3 Is used to program memory arrayProgramming of the memory can be delayed to one oflast process stepsDigital Integrated Circuits Prentice Hall 1995 MemoryMOS NOR ROM LayoutBasic x 7 WL[0]WL[1]WL[2]WL[3]Metal1 over diffusionThreshold raisingimplantBL[0]BL[1]BL[2]BL[3]Polysi liconGND (diffusion)Threshold raising implants disable transistorsDigital Integrated Circuits Prentice Hall 1995 MemoryMOS NAND ROMWL[0]WL[1]WL[2]WL[3]BL[0]BL[1]BL[2]BL [3]VDDPull-up devicesAll word lines high by default with exception of selected rowDigital Integrated Circuits Prentice Hall 1995 MemoryMOS NAND ROM LayoutBasic cell5 x 6 Threshold implantPolysiliconDiffusionloweringNo contact to VDD or GND necessary;Loss in performance compared to NOR ROMdrastically reduced cell sizeDigital Integrated Circuits Prentice Hall 1995 MemoryEquivalent Transient Model for MOS NORROMVDDWLBL rwordcwordCbitModel for NOR ROMWord line parasiticsResistance/cell: (7/2) x 10 /q = 35 Wire capacitance/cell: (7 2 ) ( )2 + 2 (7 ) = fFGate Capacitance/cell: (4 2 ) ( )2 = line parasitics:Resistance/cell: ( ) x /q = (which is negligible)Wire capacitance/cell: ( 4 ) ( )2 + 2 ( ) = fFDrain capacitance/cell.

4 ((3 4 ) ( )2 + 2 3 ) + 4 = fFDigital Integrated Circuits Prentice Hall 1995 MemoryEquivalent Transient Model for MOS NANDROMVDDWLBL rwordcwordCLrbitcbitModel for NAND ROMWord line parasitics:Resistance/cell: (6/2) x 10 /q = 30 Wire capacitance/cell: (6 2 ) ( )2 + 2 (6 ) = fFGate Capacitance/cell: (3 2 ) ( )2 = line parasitics:Resistance/cell: 10 k , the average transistor resistance over the range of capacitance/cell: Included in diffusion capacitanceSource/Drain capacitance/cell: ((3 3 ) ( )2 + 2 3 ) + (3 2 ) ( )2 = fFDigital Integrated Circuits Prentice Hall 1995 MemoryPropagation Delay of NOR ROMWord line delayConsider the 512 512 case.

5 The delay of the distributed rc-line containing Mcells can be approximated using the expressions derived in Chapter = (rword cword) M2 = (35 ( + ) fF) 5122 = 20 nsecBit line delayAssume a ( ) pull-down device and a (8 ) pull-up transistor. The bitline switches between 5 V and V. Cbit = 512 ( + ) fF = pFIavHL = 1/2 ( ) ( 10-6)(( )2/2 + ( - ( )2/2)) - 1/2 (8 ) ( 10-6) ( - ( )2/2) = mAtHL = ( pF V) / mA = nsecThe low-to-high response time can be computed using a similar approach. tLH = ( pF V) / mA = nsecDigital Integrated Circuits Prentice Hall 1995 MemoryDecreasing Word Line DelayMetal bypassPolysilicon word lineK cellsPolysilicon word lineWLDriver(b) Using a metal bypass(a) Driving the word line from both sidesMetal word lineWL(c) Use silicidesDigital Integrated Circuits Prentice Hall 1995 MemoryPrecharged MOS NOR ROMWL[0]WL[1]WL[2]WL[3]BL[0]BL[1]BL[2]BL [3]GNDGNDVDDP recharge devices prePMOS precharge device can be made as large as necessary,but clock driver becomes harder to Integrated Circuits Prentice Hall 1995 MemoryFloating-gate transistor (FAMOS)SourceDrainGateFloating gatetoxtoxSubstraten+n+p(a) Device cross-sectionSDG(b)

6 Schematic symbolDigital Integrated Circuits Prentice Hall 1995 MemoryFloating-Gate Transistor ProgrammingDS20 V20 VDS0 V0 V10 V 5 V 5 VDS5 V5 V VAvalanche programming voltageleaves charge results inhigher Integrated Circuits Prentice Hall 1995 MemoryFLOTOX EEPROMS ourceDrainGateFloating gateSubstraten+n+10 nm20-30 nm(a) Flotox transistorVGDI(b) Fowler-Nordheim I-V characteristic10 V 10 VpBLWLVDD(c) EEPROM cell during a read operationDigital Integrated Circuits Prentice Hall 1995 MemoryFlash EEPROMn+ drainn+ sourcep-substrateControl gateFloating gateprogrammingerasureThin tunneling oxideDigital Integrated Circuits Prentice Hall 1995 MemoryCross-sections of NVM cellsEPROMF lashCourtesy IntelDigital Integrated Circuits Prentice Hall 1995 MemoryCharacteristics of State-of-the-artNVMD igital Integrated Circuits Prentice Hall 1995 MemoryRead-Write MEMORIES (RAM) STATIC (SRAM) DYNAMIC (DRAM)Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferentialPeriodi c refresh requiredSmall (1-3 transistors/cell)

7 SlowerSingle EndedDigital Integrated Circuits Prentice Hall 1995 Memory6-transistor CMOS SRAM CellVDDQQM1M3M4M2M5 BLWLBLM6 Digital Integrated Circuits Prentice Hall 1995 MemoryCMOS SRAM Analysis (Write)VDDQ = 1Q = 0M1M4M5BL = 1 WLBL = 0M6 VDDknM6,VDDVTn ()VDD2-----------VDD28----------- kpM4,VDDVTp ()VDD2-----------VDD28----------- =knM5,2--------------VDD2-----------VTnV DD2----------- 2knM1,VDDVTn ()VDD2-----------VDD28----------- =(W/L)n,M5 10 (W/L)n,M1(W/L)n,M6 (W/L)p,M4 Digital Integrated Circuits Prentice Hall 1995 MemoryCMOS SRAM Analysis (Read)VDDQ = 1Q = 0M1M4M5 BLWLBLM6 VDDVDDVDDCbitCbitknM5,2---------------VD D2------------VTnVDD2------------ 2knM1,VDDVTn ()VDD2------------VDD28------------ =(W/L)n,M5 10 (W/L)n,M1(supercedes read constraint)

8 Digital Integrated Circuits Prentice Hall 1995 Memory6T-SRAM LayoutVDDGNDQQWLBLBLM1M3M4M2M5M6 Digital Integrated Circuits Prentice Hall 1995 MemoryResistance-load SRAM CellVDDQQM1M2M3 BLWLBLM4 RLRLS tatic power dissipation -- Want RL largeBit lines precharged to VDD to address tp problemDigital Integrated Circuits Prentice Hall 1995 Memory3-Transistor DRAM CellM2M1BL1 WWLBL2M3 RWLCSXWWLRWLXBL1BL2 VDD-VT VVDDVDD-VTNo constraints on device ratiosReads are non-destructiveValue stored at node X when writing a 1 = VWWL-VTnDigital Integrated Circuits Prentice Hall 1995 Memory3T-DRAM LayoutBL2BL1 GNDRWLWWLM3M2M1 Digital Integrated Circuits Prentice Hall 1995 Memory1-Transistor DRAM CellCSM1 BLWLCBLWLXBLVDD VTVDD/2 VDDGNDW rite "1"Read "1"sensingVDD/2 VVBLVPRE VBITVPRE ()CSCSCBL+------------------------==Writ e: CS is charged or discharged by asserting WL and : Charge redistribution takes places between bit line and storage capacitanceVoltage swing is small; typically around 250 Integrated Circuits Prentice Hall 1995 MemoryDRAM Cell Observations1T DRAM requires a sense amplifier for each bit line, due to charge redistribution memory cells are single ended in contrast to SRAM read-out of the 1T DRAM cell is destructive.

9 Read and refresh operations are necessary for correct 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than Integrated Circuits Prentice Hall 1995 Memory1-T DRAM Cell(a) Cross-section(b) LayoutDiffusedbit linePolysiliconplateM1 wordlineCapacitorPolysilicongateMetal word lineSiO2n+Field OxideInversion layerinduced by plate biasn+polypolyUsed Polysilicon-Diffusion CapacitanceExpensive in AreaDigital Integrated Circuits Prentice Hall 1995 MemorySEM of poly-diffusion capacitor 1T-DRAMD igital Integrated Circuits Prentice Hall 1995 MemoryAdvanced 1T DRAM CellsCell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateTrench CellStacked-capacitor CellCapacitor dielectric layerCell plateWord lineInsulating LayerIsolationTransfer gateStorage electrodeDigital Integrated Circuits Prentice Hall 1995 MemoryPeriphery Decoders Sense Amplifiers Input/Output Buffers Control

10 / Timing CircuitryDigital Integrated Circuits Prentice Hall 1995 MemoryRow DecodersCollection of 2M complex logic gatesOrganized in regular and dense fashion(N)AND DecoderNOR DecoderDigital Integrated Circuits Prentice Hall 1995 MemoryDynamic DecodersWL3 GNDGNDP recharge devicesWL2WL1WL0 VDD A0A0A1A1A0A0A1A1 VDDVDDVDDVDD WL3WL2WL1WL0 Dynamic 2-to-4 NOR decoder2-to-4 MOS dynamic NAND DecoderPropagation delay is primary concernDigital Integrated Circuits Prentice Hall 1995 MemoryA NAND decoder using 2-input pre-decodersA0A1A0A1A0A1A0A1A2A3A2A3A2A3 A2A3A1A0A0A1A3A2A2A3WL0WL1 Splitting decoder into two or more logic layersproduces a faster and cheaper implementationDigital Integrated Circuits Prentice Hall 1995 Memory4 input pass-transistor based columndecoderBL0BL1BL2BL3DA0A1S0S1S2S3 2 input NOR decoderAdvantage.