Semiconductor Process and Manufacturing Technologies …

1 Semiconductor Process and Manufacturing Technologies for 90-nm Process Generation 90 Semiconductor Process and Manufacturing Technologiesfor 90-nm Process GenerationOVERVIEW: Hitachi is actively working on the miniaturization andstandardization of CMOS (complementary metal-oxide Semiconductor )devices and on the establishment of a CMOS platform. This will enableHitachi to share IP (intellectual property), a design asset. Furthermore, inconjunction with this platform, Hitachi will develop core devices other thanCMOS devices and combine rich IP to provide customers with system-on-a-chip products as an optimal solution.

2 Hitachi is adopting an APC(advanced Process control) technology to reduce variation in its processand Manufacturing Technologies . It also aims to support the production of asmall volume of many products and to respond quickly to market andcustomer needs, especially through the full single-wafer processing line for300-mm wafers at Trecenti Technologies , Inc. (TTI).Takafumi TokunagaKatsutaka KimuraJun NakazatoFumiyuki KanaiINTRODUCTIONIN the Semiconductor industry, the miniaturization ofsemiconductor devices has enabled developing high-performance and low-cost products by increasing thenumber of logic circuits that can be integrated on anLSI (large-scale integration) and by raising theoperating frequency.

3 In this environment, the designerneeds to develop large-scale, complex, and high-speedsystems in a relatively short time, and sharing the IPis indispensable to making this work more IP sharing requires that design rules andlibraries be standardized, and to this end, Hitachi hasbeen actively promoting the miniaturization andstandardization of a CMOS platform in cooperationFig. 1 System-on-a-chip as an Optimal the System-on-a-chip era, customers must be provided with system LSIs. This requires close interfacingamong design, device processes, and : central processing unitDesignDevice processesManufacturingSystem-on-a-chipCM OS platformStandardization300-mm wafersFull single-wafer processingScalabilityMiniaturizationComb ined processesCreating a best solutionNon-volatile memoryIPIPCPUA nalog signal processingHigh-frequency moduleStandard busStandard CMOS deviceOther devicesHitachi Review Vol.

4 51 (2002), No. 4 91with Semiconductor Technology Academic ResearchCenter (STARC) in the same time, Hitachi has been independentlydeveloping core devices other than CMOS devices andadding to IPs to provide customers with optimalsystem-on-a-chip products. For Manufacturing thesystem-on-a-chip products, Hitachi is pursuing aproduction format centered about TTI, a company thathas a full single wafer processing line for 300-mmwafers, to respond quickly to market and this report, we focus on CMOS devices, whosestandardization is progressing, and describe themanufacturing Technologies for minimizing featuresizes with the aim of improving device examine, in particular, how variation in devicecharacteristics increases relative to the variation inmanufacturing Technologies when shrinking featuresizes.

5 And outline APC technology as a countermeasureto this OF CMOS DEVICESA chieving High Performance by MiniaturizingA CMOS device is a switch that turns the currentbetween the source and the drain on and off. The basicperformance of this switch can be determined byexamining whether a large drive current is made toflow when the switch is on and whether the leak currentcan be reduced when the switch is most effective way of obtaining a large drivecurrent when the switch is on is to reduce the gatelength and to make the gate insulation-film thinner[Fig. 2 (a)]. In other words, the drive current increasesby reducing the distance covered by carriers in eachchannel and by increasing the number of mobility is also known to be greatly affectedby the stress applied to channels1), and two keymethods to improve mobility are now being first method controls the stress applied to theinsulation film covering the device, and the secondmethod grows a Si substrate on a SiGe crystal andapplies strain to the Si has successfully fabricated a prototypeCMOS device with a 50-nm gate length2) and one usinga strained Si layer3) [Fig.]

6 2 (b) and (c)].Elemental Technologies for Miniaturization (1) International Technology Roadmap forSemiconductors (ITRS) 2001 edition for CMOS devicesTable 1 shows the 2001 version of the ITRS forCMOS miniaturization. It describes the ongoingreduction of the gate dimensions and the thinning ofthe gate insulation film with the node size decreasingfrom 130 to 90 nm. Mass production of devices with90-nm nodes is expected to start sometime in 2003 or2004, and we are now aiming at establishingmanufacturing Technologies that can produce productsFig. 2 CMOS Device basic performance of a CMOS device is determined bywhether a large drive current is made to flow when the switch ison and whether leak current can be reduced when the switch 1.

7 ITRS: 2001 Edition for CMOS DevicesThe 90-nm era is expected to begin sometime in 2003 or 2004.(1) Reduction of gate length(2) Thinning of gate insulation film (3) Control of channel stress(c) Structure of strained Si layer(b) Prototype 50-nm CMOS device(a) Key points of miniaturizationSiNSpacerCoSi2 CoSi2Si substrate50 nmStrained Si layerSiGe layer2 mSi (100) substrateTechnology node(nm)Gate dimensions(nm)Gate-dimension accuracy (3 ) (nm)Gate insulation-film thickness (EOT)(nm)Wiring pitch (nm) bottom layerWiring pitch (nm) intermediate layerPermittivity (k) of inter-layer insulation filmEOT: effective oxide thickness2001200220032004130 [International Technology Roadmap for semiconductors (ITRS): 2001 Edition] Semiconductor Process and Manufacturing Technologies for 90-nm Process Generation 92with gate dimensions under 50 nm and an insulationfilm thinner than nm.

8 (2) Fine-processing technologiesThe core Technologies behind fine processing arelithography and dry etching. In lithography, theresolution can be improved by shortening thewavelength of the light source in the exposureequipment and by increasing the NA (numericalaperture) of the lens. For 90-nm nodes, the plan is toadopt an ArF light source (wavelength: 193 nm) and alens with an NA of or greater. The developmentof resist material for ArF use is also progressing andstabilizing and resolving a 90-nm resist pattern hasalready become possible. Our future goal is to developa lens with an NA of and resist material that ishighly resistant to dry , while phase shifting and OPC (opticalproximity correction) are becoming indispensabletechniques for raising the resolution performance, theincrease in mask-drawing data has resulted in adramatic jump in mask costs.

9 Consequently, drasticmeasures in Manufacturing processes and equipmentthat can significantly decrease mask cost are dry etching technology, a slimming Process for reducing the resist dimensions has becomenecessary considering that the target gate length takeson dimensions less than the resolution of the exposureequipment4). The gate-electrode material should nowcontain SiGe polycrystal to reduce depletion, and it isnecessary to achieve a rectangular cross-sectionalshape without causing dimensional , obtaining a highly accurate impurity-concentration distribution in a CMOS device nowrequires accurate processing in the sidewall spacers.

10 (3) Gate insulation-film technologyBecause the thickness of the gate insulation filmswill decrease to nm or less in 90-nm CMOS devicesas shown in Table 1, the tunnel current, which is oneleak-current component when the switch is off, willflow through the gate insulation film, which isproblematic. To decrease this tunnel current, the useof high dielectric constant film instead of silicon-oxidefilm is now being studied. This alternative has not beenfully adopted yet, however, as good electricalcharacteristics cannot be ensured at the interfacebetween Si and the high dielectric constant film. Forthis reason, we are developing plasma nitridation thatcan improve controlling the nitrogen concentrationdistribution in the nitridation of conventional silicon-oxide film.