SN74LV1T34 Single Power Supply Single Buffer GATE …

1 SN74LV1T34 Single Power Supply Single Buffer GATE CMOS Logic Level Shifter1 Features Latch-Up Performance Exceeds 250 mAPer JESD 17 Single - Supply voltage translator at 5-V, , , and VCC Operating range of V to V Up translation: V(1) to V at VCC V(1) to V at VCC V(1) to V at VCC V to V at VCC Down translation: V to V at VCC V to V at VCC V to V at VCC Logic output is referenced to VCC Output drive: 8 mA output drive at 5 V 7 mA output drive at V 3 mA output drive at V Characterized up to 50 MHz at VCC 5V Tolerance on input pins 40 C to 125 C operating temperature range Supports standard logic pinouts CMOS output B compatible with AUP1G and LVC1G families 12 Applications Telecom Portable applications Servers PC and notebooks3 DescriptionThe SN74LV1T34 is a Single Buffer gate with reduced input thresholds to support voltage translation Information(1) PART NUMBERPACKAGEBODY SIZE (NOM) SN74LV1T34 DBV (SOT-23, 5) mm mmDCK (SC70, 5)

2 Mm mm(1)For all available packages, see the orderable addendum at the end of the data LogicVcc = = = LogicVcc = , , , = = min = min = min = max = , , = Thresholds for to Translation1 Refer to the VIH/VIL and output drive for lower VCC DECEMBER 2013 REVISED JUNE 2022An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION of Contents1 Revision Related Pin Configuration and Absolute Maximum ESD Recommended Operating Thermal Electrical Switching Operating Typical Parameter Measurement Detailed Functional Block Feature Device Functional Power Supply Layout Device and Documentation Receiving Notification of Documentation Support Electrostatic Discharge Mechanical, Packaging, and Orderable Revision HistoryNOTE.

3 Page numbers for previous revisions may differ from page numbers in the current from Revision A (February 2014) to Revision B (June 2022)Page Updated the numbering format for tables, figures, and cross-references throughout the Deleted DPW package throughout the data Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and Functions section, Detailed Description section, Power Supply Recommendations section, Layout section, Receiving Notification of Documentation Updates section, and Community Resources Deleted function table for the Supply Vcc = V test case.

4 12 Changes from Revision * (December 2013) to Revision A (February 2014)Page Updated document formatting..1 Updated VCC values for VIH parameter in the Electrical Characteristics DECEMBER 2013 REVISED JUNE Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: SN74LV1T345 Related ProductsDEVICEPACKAGEDESCRIPTIONSN74LV1T 00 DCK, DBV2-Input Positive-NAND GateSN74LV1T02 DCK, DBV2-Input Positive-NOR GateSN74LV1T04 DCK, DBVI nverter GateSN74LV1T08 DCK, DBV2-Input Positive-AND GateSN74LV1T17 DCK, DBVS ingle Schmitt-Trigger Buffer GateSN74LV1T14 DCK, DBVS ingle Schmitt-Trigger Inverter GateSN74LV1T32 DCK, DBV2-Input Positive-OR GateSN74LV1T34 DCK, DBVS ingle Buffer GateSN74LV1T86 DCK, DBVS ingle 2-Input Exclusive-Or GateSN74LV1T125 DCK, DBVS ingle Buffer Gate with 3-state OutputSN74LV1T126 DCK.

5 DBVS ingle Buffer Gate with 3-state OutputSN74LV4T125 RGY, PWQuadruple Bus Buffer Gate With 3-State DECEMBER 2013 REVISED JUNE 2022 Copyright 2022 Texas Instruments IncorporatedSubmit Document Feedback3 Product Folder Links: SN74LV1T346 Pin Configuration and YFigure 6-1. DCK or DBV Package, 5-Pin SC70 or SOT-23 (Top View)Table 6-1. Pin FunctionsPINTYPE(1) Not internally connectedA2 IInput AGND3 GGroundY4 OOutput YVCC5 PPositive Supply (1)I = Input, O = Output, I/O = Input or Output, G = Ground, P = DECEMBER 2013 REVISED JUNE Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links.

6 SN74LV1T347 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted)(1)MINMAXUNITVCCS upply voltage range voltage range(2) range applied to any output in the high or low state(2) + clamp currentVI < 0 20mAIOKO utput clamp currentVO < 0 or VO > VCC 20mAIOC ontinuous output current 25mAContinuous current through VCC or GND 50mATJJ unction temperature150 CTstgStorage temperature 65150 C(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.

7 Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are ESD RatingsVALUEUNITV(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 VMachine Model (MM), per JEDEC specification 200 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) 1000(1)JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2)JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control DECEMBER 2013 REVISED JUNE 2022 Copyright 2022 Texas Instruments IncorporatedSubmit Document Feedback5 Product Folder Links.

8 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)MINMAXUNITVCCS upply voltage0 VCCVIOHHigh-level output currentVCC = V 3mAVCC = V 5 VCC = V 7 VCC = V 8 IOLLow-level output currentVCC = V3mAVCC = V5 VCC = V7 VCC = V8 t/ vInput transition rise or fall rateVCC = V20ns/VVCC = V or V20 VCC = V20 TAOperating free-air temperature 40125 C(1)All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number Thermal InformationTHERMAL METRIC(1)DBVDCKUNIT5 PINS5 PINSR JAJunction-to-ambient thermal resistance206252 C/W(1)For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise noted)

9 PARAMETERTEST CONDITIONSVCCTA = 25 CTA = 40 C to +125 CUNITMINTYPMAXMINTYPMAXVIHHigh-level input voltageVCC = V to = = V to = = 3 V to = = V to = input voltageVCC = V to = V to = 3 V to = V to DECEMBER 2013 REVISED JUNE Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: SN74LV1T34over recommended operating free-air temperature range (unless otherwise noted)PARAMETERTEST CONDITIONSVCCTA = 25 CTA = 40 C to +125 CUNITMINTYPMAXMINTYPMAXVOHHigh-level output voltageIOH = 20 V to VVCC = = = = = = = = = output voltageIOL = 20 V to = = = = = = leakage currentA input; VI = 0 V or VCC0 V, V, V, V, 1 AICCS tatic Supply currentVI = 0 V or VCC,IO = 0.

10 Open on V110 V110 ICCA dditional static Supply currentOne input at V or V,Other inputs at 0 or VCC,IO = input at V or VOther inputs at 0 or VCC,IO = V1010 ACiInput capacitanceVI = VCC or V210210pFCoOutput capacitanceVO = VCC or Switching Characteristicsover recommended operating free-air temperature range (unless otherwise noted) (see Parameter Measurement Information)PARAMETERFROM(INPUT)TO(OUTPU T)FREQUENCY(TYP)VCCCLTA = 25 CTA = 65 C to 125 CUNITMINTYPMAXMINTYPMAXtpdAny InYDC to 50 V15 V15 pF4758ns30 to 25 V15 to 15 V15 DECEMBER 2013 REVISED JUNE 2022 Copyright 2022 Texas Instruments IncorporatedSubmit Document Feedback7 Product Folder Links: Operating CharacteristicsTA = 25 CPARAMETERTEST CONDITIONSVCCTYPUNITCpdPower dissipation capacitancef = 1 MHz and 10 V V V V Typical CharacteristicsTime (ns)Voltage (V) 7-1.