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1 Successive Approximation ADC1 Successive Approximation ADCA Successive Approximation ADC is a type of analog-to-digital converter that converts a continuous analogwaveform into a discrete digital representation via a binary search through all possible quantization levels beforefinally converging upon a digital output for each diagramSuccessive Approximation ADC Block DiagramKey DAC = Digital-to-Analog converter EOC = end of conversion SAR = Successive Approximation register S/H = sample and hold circuit Vin = input voltage Vref = reference voltageAlgorithmThe Successive Approximation Analog todigital converter circuit typically consists offour chief sample and hold circuit to acquirethe input voltage (Vin). analog voltage comparator thatcompares Vin to the output of theinternal DAC and outputs the result of the comparison to the Successive Approximation register (SAR).

2 Successive Approximation register subcircuit designed to supply an approximate digital code of Vin to theinternal internal reference DAC that, for comparison with V, supplies the comparator with an analog voltage equalto the digital code output of the Successive Approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. Thiscode is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparatorcircuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes theSAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuingthis binary search until every bit in the SAR has been tested. The resulting code is the digital Approximation of thesampled input voltage and is finally output by the SAR at the end of the conversion (EOC).

3 Mathematically, let Vin = xVref, so x in [-1, 1] is the normalized input voltage. The objective is to approximatelydigitize x to an accuracy of 1/2n. The algorithm proceeds as Approximation x0 = Approximation xi = xi-1 - s(xi-1 - x) , s(x) is the signum-function(sgn(x)) (+1 for x 0, -1 for x < 0). It follows using mathematical induction that|xn - x| 1 shown in the above algorithm, a SAR ADC input voltage source reference voltage source Vref to normalize the Approximation DAC to convert the ith Approximation xi to a Comparator to perform the function s(xi - x) by comparing the DAC's voltage with the input Register to store the output of the comparator and apply xi-1 - s(xi-1 - x) Successive Approximation ADCC harge Scaling DACOne of the most common implementationsof the Successive Approximation ADC, thecharge-redistribution successiveapproximation ADC, uses a charge scalingDAC.

4 The charge scaling DAC simplyconsists of an array of individually switchedbinary-weighted capacitors. The amount ofcharge upon each capacitor in the array isused to perform the aforementioned binarysearch in conjunction with a comparatorinternal to the DAC and the successiveapproximation , the capacitor array is completely discharged to the offset voltage of the comparator, VOS. This stepprovides automatic offset cancellation( The offset voltage represents nothing but dead charge which can'tbe juggled by the capacitors). , all of the capacitors within the array are switched to the input signal, vIN. The capacitors now have acharge equal to their respective capacitance times the input voltage minus the offset voltage upon each the third step, the capacitors are then switched so that this charge is applied across the comparator's input,creating a comparator input voltage equal to , the actual conversion process proceeds.

5 First, the MSB capacitor is switched to VREF, whichcorresponds to the full-scale range of the ADC. Due to the binary-weighting of the array the MSB capacitorforms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now -vIN plusVREF/2. Subsequently, if vIN is greater than VREF/2 then the comparator outputs a digital 1 as the MSB,otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparatorinput voltage converges to the offset voltage, or at least as close as possible given the resolution of the bits simulation of a capacitive ADCS plit capacitor arrayDuring the binary search process, the charge redistribution DACconsumes power from the reference source for charging. There aremany energy efficient ways of charging the DAC and split capacitorarray is one of the way in which MSB capacitor is split to look like theremaining DAC for small energy Approximation ADC3 Use with non-ideal analog circuitsWhen implemented as an analog circuit - where the value of each Successive bit is not perfectly 2^N ( , , , , etc.)

6 - a Successive Approximation approach might not output the ideal value because the binary searchalgorithm incorrectly removes what it believes to be half of the values the unknown input cannot be. Depending onthe difference between actual and ideal performance, the maximum error can easily exceed several LSBs, especiallyas the error between the actual and ideal 2^N becomes large for one or more bits. Since we don't know the actualunknown input, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC bevery close to the ideal 2^N values; otherwise, we cannot guarantee a best match conversion time is equal to the "n" clock cycle period for an n-bit ADC. Thus conversion time is very example for a 10-bit ADC with a clock frequency of 1 MHz, the conversion time will be only 10*10^-6 time is constant and independent of the amplitude of analog signal V to the base AReferences R.

7 J. Baker, CMOS Circuit Design, Layout, and Simulation, Third Edition, Wiley-IEEE, 2010. ISBN978-0-470-88132-3 External links Understanding SAR ADCs [1]References[1]http:/ / www. maxim-ic. com/ appnotes. cfm/ appnote_number/ 1080/ CMP/ WP-50 Article Sources and Contributors4 Article Sources and ContributorsSuccessive Approximation ADC Source: Contributors: Amalas, B Pete, BD2412, Biscuittin, Braincricket, Btyner, EAderhold, Ec5618,Eus Kevin, Ferdinand Pienaar, Firebat08, Jeff3000, LittleCreature, Mandarax, Michael Hardy, Nolelover, Oli Filth, Omar El-Sewefy, Pankaj Warule, Pjrm, R'n'B, Salvar, SeymourSycamore,Smyth, Tabletop, Whiteflye, Zeeyanwiki, 65 anonymous editsImage Sources, Licenses and ContributorsFile:SA ADC block Source: License: Creative Commons Attribution-Sharealike Contributors:White Source: License: Creative Commons Attribution-Sharealike Contributors: White Source: License: Public Domain Contributors: GonzaljLicenseCreative Commons Attribution-Share Alike