TUSB9261 USB 3.0 to SATA Bridge datasheet (Rev. I)

1 USB SSPHYUSB HS/FSPHYUSB M3 ROMRAM64 kBWatchdogTimerTimerSCI(UART)GPIOPWMSATA IIPHYSATAAHCISSTX+SSTX-DP/DMSSRX+SSRX-SA TATX+SATATX-SATARX+SATARX-UartRXGPIO[11: 0]SPISCLKDATA_OUTDATA_INCS[2:0] PathRAM80 kBUSB_R1 USB_R1 RTNVBUSUartTXPWM[1:0]ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityReferenceDesignAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand MARCH2011 REVISEDMARCH2016 TUSB9261 USB to SATA Bridge11 Features1 UniversalSerialBus (USB) Compliant TID340730020 IntegratedTransceiverSupportsSS/HS/FSSig naling Best-in-ClassAdaptiveEqualizer Allowsfor GreaterJitterTolerancein theReceiver USBC lassSupport USBA ttachedSCSIP rotocol(UASP) USBMassStorageClassBulk-OnlyTransport(BO T) Supportfor ErrorConditionsPer the 13 Cases(Definedin the BOTS pecification) USBB ootabilitySupport USBH umanInterfaceDevice(HID)

2 SupportsFirmwareUpdateVia USB,UsingaTI ProvidedApplication SATAI nterface Gen1i,Gen1m,Gen2i,and Gen2m Supportfor Mass-StorageDevicesCompatibleWiththe ATA/ATAPI-8 Specification IntegratedARMC ortexM3 Core CustomizableApplicationCodeLoadedfromEEP ROMby SPI Interface Two AdditionalSPI Port ChipSelectsforPeripheralConnection Up to 12 GPIO sfor End-UserConfiguration Two GPIO shavePWMF unctionalityforLEDB linkSpeedControl SerialCommunicationsInterfacefor Debug(UART) GeneralFeatures IntegratedSpreadSpectrumClockGenerationE nablesOperationfroma SingleLow-CostCrystalor ClockOscillator Supports40 MHz A JTAGI nterfaceis Usedfor Availablein a FullyRoHS-CompliantPackage2 Applications ExternalHDD/SSD ExternalDVD ExternalCD HDD-BasedPortableMediaPlayer3 DescriptionTheTUSB9261is anARM Cortex to necessaryhardwareandfirmwaretoimplementa USBattachedSCSI protocol(UASP)-compliantmassstoragedevic esuitablefor bridgingharddisk drives(HDD),solidstatedisk drives(SSD),opticaldrives,and a UASP support,the firmwareimplementsthe massstorageclassBOTand USBHID (1)PARTNUMBERPACKAGEBODYSIZE(NOM)TUSB926 1 HTQFP(64) (1) For all availablepackages,see the orderableaddendumatthe end of the MARCH2011.

3 TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporatedTableof Contents1 Pin Configurationand ElectricalCharacteristicsfor Applicationand Deviceand Mechanical,Packaging,and RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (July2015)to RevisionIPage Changedthe CDMvaluein theESDR atingstableFrom:5000To: (October2014)to RevisionHPage MovedTstgfromHandlingRatingstabletoAbsol uteMaximumRatingsand 7 Updatedthe frequencyfor the USB2and USB3to 5 Hz and 10 Hz, (March2014)to RevisionGPage Updatedsupportedfrequencyto 40 UpdatedsupportedfrequencyinClockand Updatedthe frequencyfor the clockto 40 Updatedthe frequencyfor the crystalto 40 Updatedoscillationfrequencyand / GPIO10 SPI_CS2 / GPIO11 JTAG_TCKJTAG_TDIJTAG_TDOJTAG_TMSJTAG_TRS TzGPIO9 / UART_TXGPIO8 / UART_RXGPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 PWM1 PWM0 VDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDD33 VDD33 VDD33 VDDA33 VDDA33 VDDA33 VDDA33 VSSVSSXIVSSOSCNCNC123456 7 8 9 1011 12131415 MARCH2011 REVISEDMARCH2016 ProductFolderLinks.

4 TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporated5 Pin Configurationand FunctionsPVPP ackage48-PinHTQFPTop View4 TUSB9261 SLLSE67I MARCH2011 : TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporatedSignalD escriptions I/O DefinitionsI/O TYPEDESCRIPTIONII nputOOutputI/OInput/outputPUInternalpull upresistorPDInternalpulldownresistorPWRP owersignalClockand resetbringsall of the TUSB9261internalregistersto asserted,the deviceis terminalis the crystalinputfor the inputmay alternatelybe drivenby the outputof an crystal,a 1-M feedbackresistoris requiredbetweenX1 and terminalis the crystaloutputfor the XI is drivenby anexternaloscillator,this pin may be left crystal,a 1-M feedbackresistoris requiredbetweenX1 and [1:0]31, oscillatorinputfrequencyand are usedtoconfigurethe correctPLL field encodingis as follows.

5 FREQSEL[1]FREQSEL[0]INPUTCLOCKFREQUENCY1 140 MHz(1)Notethat the defaultfirmwareand referencedesignfor the TUSB9261havethe SATATXP/TXMswappedfor easeof routingin you plan to use the TI defaultfirmwarepleasereviewthe referencedesignin theTUSB9261 DEMOUser s Guide(SLLU139) for (1) (positive)SATA_TXM56 OSerialATAtransmitterdifferentialpair (negative)SATA_RXP60 ISerialATAreceiverdifferentialpair (positive)SATA_RXM59 ISerialATAreceiverdifferentialpair (negative) (positive)USB_SSTXM42 OSuperSpeedUSBtransmitterdifferentialpai r (negative)USB_SSRXP46 ISuperSpeedUSBreceiverdifferentialpair (positive)USB_SSRXM45 ISuperSpeedUSBreceiverdifferentialpair (negative)USB_DP36I/OUSB high-speeddifferentialtransceiver(positi ve)USB_DM35I/OUSB high-speeddifferentialtransceiver(negati ve)USB_VBUS50 IUSBbus 10-k 1% resistorshouldbe connectedbetweenR1 and MARCH2011 REVISEDMARCH2016 ProductFolderLinks: TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporatedSerialP eripheralInterface(SPI) clockSPI_DATA_OUT18 OPUSPI masterdataoutSPI_DATA_IN20 IPUSPI masterdatainSPI_CS021 OPUP rimarySPI chip selectfor flashRAMSPI_CS2/23I/OPUSPI chip selectfor usedfor SPI chip select,this pin may be usedas a general- chip selectfor usedfor SPI chip select,this pin may be usedas a general- (1)PWMpulldownresistorsare disabledby firmwaremodificationis requiredto turn themon.

6 All otherinternalpull up/downresistorsare enabledby ,GPIO,and clockJTAG_TDI26 IPUJTAG test datainJTAG_TDO27 OPDJTAG test dataoutJTAG_TMS28 IPUJTAG test modeselectJTAG_TRSTz29 IPDJTAG test resetGPIO9/UART_TX6I/ terminalcan be configuredas a GPIOor as the transmitterfor pin defaultsto a terminalcan be configuredas a GPIOor as the receiverfor a pin defaultsto a general-purposeinput/outputsGPIO615I/OPD GPIO514I/OPDGPIO413I/OPDGPIO311I/OPDGPIO 210I/OPDGPIO19I/OPDGPIO08I/OPDPWM02 OPD(1)Pulse-widthmodulation(PWM).Can be usedto (1)6 TUSB9261 SLLSE67I MARCH2011 : TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporatedPoweran d usinga crystal,this shouldnot be connectedto a oscillator,this shouldbe connectedto ThermalpadNC37 No connect, MARCH2011 REVISEDMARCH2016 ProductFolderLinks: TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporated6 (unlessotherwisenoted)MINMAXUNITVDDS teady-statesupplyvoltage 55150 C(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.

7 (2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (HBM),per ANSI/ESDA/JEDECJS001(1) 2000 VChargeddevicemodel(CDM),per JESD22-C101(2) (unlessotherwisenoted) CIndustrialversion 4085 TJOperatingjunctiontemperaturerange 40100 C(1)For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC PackageThermalMetricsapplicationreport, (1) TUSB9261 UNITPVP(HTQFP)64 PINSR C/WR JC(top)Junction-to-case(top) C/WR C/W C/W C/WRJ C(bot)Junction-to-case(bottom) C/W8 TUSB9261 SLLSE67I MARCH2011 : TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016, ElectricalCharacteristicsfor (unlessotherwisenoted)PARAMETERTESTCONDI TIONSMINTYPMAXUNITDRIVERTRR isetime5 time5 V, TJ= 25 C6mAIOHHigh-leveloutputcurrentVDD33= V, TJ= 25 C 6mAVOLLow-leveloutputvoltageIOL= 2 2 (TRand TF)10nsIIInputcurrentVI= 0 V to VDD335 ACII nputcapacitanceVDD33= V, TJ= 25 (1)Transferringdataby SS USBto a SSDSATAGen II SATA powermanagement,U0 only.

8 (2)SATAGen II SSDattachedno SATA powermanagement,U3 only.(3)All (mA)(1)TYPICALSUSPENDCURRENT(mA)(2)VDD11 291153 VDD33(3)6528(1)Transferringdatavia HS USBto a SSDSATAGen II SATA powermanagement.(2)SATAGen II SSDattachedno SATA powermanagement.(3)All (mA)(1)TYPICALSUSPENDCURRENT(mA)(2)VDD11 172153 VDD33(3) MARCH2011 REVISEDMARCH2016 ProductFolderLinks: TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporated(1)Sigm avalueassumingGaussiandistribution(2)Aft erapplicationof JTF(3)Calculatedas RJ+ DJ(4)Absolutephasejitter (p-p) shouldbe tied to the XO shouldbe left connectedto the 40-MHzclockcan be inputcapacitanceTJ= 25 5050ppmTdutyDutycycle45%50%55%TR/TFRise/ falltime20%to 80%6nsRJReferenceclockJTF (1 sigma)(1)(2) (totalp-p)(2)(3)25psTp-pReferenceclockji tter(Absolutep-p)(4) parallel,20-pFload capacitorshouldbe usedif a crystalsourceis be connectedto the 40-MHzcrystalcan be OOscillationfrequency40 MHzESRE quivalentseriesresistance40 MHz50 Ttosc_iFrequencytoleranceOperationaltemp erature 50ppmFrequencystability1 yearaging 50ppmCLLoadcapacitance122024pFCSHUNTC rystaland (max) (1)USB (1)PCwithUSB MARCH2011.

9 TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporated7 majorfunctionalblocksare as follows: CortexM3 microcontrollersubsystemincludingthe followingperipherals: Timeinterruptmodules,includingwatchdogti mer Universalasynchronousreceive/transmit(SC I) SPI Generalpurposeinput/output(GPIO) PWMfor supportof PWMoutputs(PWM) core(endpointcontroller)and PHY AHCI-compliantSATA controllerand integratedSATAPHY SupportingGen1i,Gen1m,Gen2i,and Gen2m Chiplevelclockgenerationand distribution Supportfor madeat eitherSuperSpeedor high speed,dependingon the globalreset,whichperformsthe initialconfigurationrequiredto load a firmwareimagefroman attachedSPI flashmemoryto firmwareis loaded,it configuresthe SATA advancedhostcontrollerinterfacehostbus adapter(AHCI)and the addition,the configurationof the AHCI includesa port reset,whichinitiatesanout of band(OOB)TX sequencefromthe AHCI link layerto determineif a deviceis connected,and if so,negotiatethe connectionspeedwith the device( Gbpsor Gbps).

10 The configurationof the USBdevicecontrollerincludescreationof the descriptors,configurationof the deviceendpointsfor supportof UASPand USBmassstorageclassBOT,allocationof memoryfor the transmitrequestblocks(TRBs),and creationof the TRBsnecessaryto transmitand receivepacketdataoverthe ,the firmwareprovidesany othercustomconfigurationrequiredfor application-specificimplementation,for example,a HID interfacefor MARCH2011 REVISEDMARCH2016 ProductFolderLinks: TUSB9261 SubmitDocumentationFeedbackCopyright 2011 2016,TexasInstrumentsIncorporatedFeature Description(continued)Afterthe USBdevicecontrollerconfigurationis complete,if a SATA devicewasdetectedduringthe AHCI configuration,the firmwareconnectsthe deviceto the USBbus whenVBUSis the specification,the TUSB9261initiallytriesto connectat successful,it entersU0;otherwise,afterthe trainingtimeout, it enablesthe DP pullupand connectsas a high-speedor full-speeddevicedependingon the speedsupportedby host or hub ,the firmwarepresentsthe BOTinterfaceas the primaryinterfaceand the UASP interfaceasthe the hoststackis UASP aware,it canenablethe UASP interfaceusingaSET_INTERFACE requestfor ,the deviceshouldtransmita deviceto host(D2H)FIS with the first D2 HFIS is receivedby the link layerand copiedto the port notifiedof the deviceconnection,it queriesthe devicefor capabilitiesusingthe deviceas appropriatefor its interfaceand featuressupported,for example,an HDDthatsupportsnativecommandqueuing(NCQ) .