Verilog HDL Coding - Cornell University

1 Verilog HDL CodingSemiconductor Reuse StandardIPMXDSRSHDL0001 SRS 01 FEB 20052 Freescale Semiconductor, Inc. 2005 Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function ordesign. Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;neither does it convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,or authorized for use as components in systems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the Freescale product could create a situation wherepersonal injury or death may occur.

2 Should Buyer purchase or use Freescale products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributorsharmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, anyclaim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescalewas negligent regarding the design or manufacture of the part.

3 Freescale and and the stylized Freescale logo are registeredtrademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. is an Equal Opportunity/Affirmative Action SemiconductorRevision HistoryVersion NumberDateAuthorSummary of JAN MAR 1999 SoCDTR evision based on SRS development process. Detailed history contained in DWG DEC 1999 SoCDTR evision based on SRS development process. Detailed history contained in DWG APR 2001 SoC-IP Design SystemsChange summary location: DEC 2001 SoC& MAR 2002 SoC&IPChanged from MCP to MIUO; Changed Motorola font batwing to batwing NOV 2002 SoC&IPChanged to reflect changes to SRS APR 2003 SoC&IPChanged to reflect changes to SRS ; added eight new paragraph FEB 2005 DEOA dded updates for SRS 01 FEB 20053 Semiconductor Reuse StandardFreescale SemiconductorTable of ContentsSection 7 Verilog HDL.

4 Information .. Documents .. Conventions .. Naming .. of HDL Code Items .. Headers .. Construct Headers .. Comments .. Style .. Partitioning and Reusability .. Practices .. Coding Techniques.. for Structured Test Techniques.. General Standards for Synthesis .. 38 SRS 01 FEB 20054 Semiconductor Reuse StandardFreescale SemiconductorSRS 01 FEB 20055 Semiconductor Reuse StandardFreescale SemiconductorList of FiguresFigure 7-1 Verilog File Header .. 20 Figure 7-2 Verilog Functions, User-Defined Primitives and Tasks Header.

5 21 Figure 7-3 Verilog Coding Format (Page 1) .. 25 Figure 7-4 Verilog Coding Format (Page 2) .. 26 Figure 7-5 Metastability Hazard Due to a Violation of this rule .. 29 Figure 7-6 Proper Use of Synchronization Register According to this rule .. 29 Figure 7-7 Scan Support for Mixed Latch/Flip-Flop Designs .. 38 SRS 01 FEB 20056 Semiconductor Reuse StandardFreescale SemiconductorSRS 01 FEB 20057 Semiconductor Reuse StandardFreescale SemiconductorList of TablesSRS 01 FEB 20058 Semiconductor Reuse StandardFreescale SemiconductorSRS 01 FEB 20059 Semiconductor Reuse StandardFreescale SemiconductorRule and Guideline ReferenceIntroductionReference InformationNaming ConventionsR most one module per fileR naming conventionsR analog, digital.

6 And mixed-signal Verilog filesR Code items naming conventionR abbreviations and additional naming conventionsR text macros include module nameR naming conventionsR naming convention - suffixesR naming convention - prefixesG signal names throughout hierarchyR name length does not exceed 32 charactersCommentsR file must contain a file header with required fieldsR constructs in file use a header with required fieldsR conventionsCode StyleR code in a tabular formatG consistent code indentation with spacesR Verilog statement per lineR port declaration per lineG port orderR internal netsG length not to exceed 80 charactersModule Partitioning and ReusabilityR accesses to nets and variables outside the scope of a moduleG use of include compiler directives should be avoidedR plugs outside of top most moduleR potentially non-portable constructsG conventions - generalG conventions - clocksModeling PracticesR hard-coded global distribution

7 NetsR asynchronous interface signalsR technology independent code for noninferred blocksSRS 01 FEB 200510 Semiconductor Reuse StandardFreescale SemiconductorR gated clock enables and direct action signalsR state of powered down signalsR control storage elementsG datapath storage elementsG synchronous design practicesR combinational feedback loopsGeneral Coding TechniquesR in condition must be a 1-bit valueR consistent ordering of bus bitsR not assign x value to signalsR reg assign in two always constructsG parameters instead of text macros for symbolic constantsR macros must not be redefinedG relationships between constantsR parameters for state encodingsG define usage includes undefR programmable base addressesR text macros for base addressesR base + offset for address generationG symbolic constants for register field valuesG ifdef nesting to three levelsG text macros for signal hierarchy pathsR are not allowedR sizes must matchR

8 Ports by name in module instantiationsR match for vector port and net/variable declarationsR connection widths must matchG ports of type inoutG parentheses in complex equationsG disables on named blocks or tasks containing nonblocking assignments with delaysG task guardsG encoding of state machines should be made through the use of case statementsR internal three-state logicG three-state outputsR multiplier must be greater than zeroStandards for Structured Test TechniquesR additional logic for scanning high-impedance devicesR PLL bypassG clock divider bypassR support logic for gated clocksR control asynchronous reset of storage elementsR transparent during scanR simultaneous master/slave latch clockingG opposing phase clocksSRS 01 FEB 200511 Semiconductor Reuse StandardFreescale SemiconductorGeneral Standards for SynthesisR always sensitivity listR clock per always sensitivity listR use synthesizable constructsR combinational logic

9 CompletelyG default values to outputs before case statementsG full_case synthesis directiveR disable in looping constructsR unbounded loopsR are not allowed in port connectionsG top-level glue logicR primitives are prohibitedR nonblocking assignments when inferring flip-flops and latchesR all unused module inputsG unused module outputsR not infer latches in functionsR of casex is not allowedR synthesis scripts are not allowedG a cycle-wide enable signal for signals with multicycle pathsG high-impedance devices explicitlyG direct instantiation of standard library cellsSRS 01 FEB 200512 Semiconductor Reuse StandardFreescale SemiconductorSRS 01 FEB 200513 Semiconductor Reuse StandardFreescale SemiconductorSection 7 Verilog HDL IntroductionThe Verilog HDL Coding standards pertain to virtual component (VC) generation and deal with namingconventions, documentation of the code and the format, or style, of the code.

10 Conformity