Verilog - Operators - Oregon State University

1 Verilog - OperatorsIVerilog Operators operate on several data types to produce an outputINot all Verilog Operators are synthesible (can produce gates)ISome Operators are similar to those in the C languageIRemember, you are making gates, not an algorithm (in most cases) Verilog - OperatorsArithmetic OperatorsIThere are two types of Operators : binary and unaryIBinary Operators :Iadd(+), subtract(-), multiply(*), divide(/), power(**), modulus(%)//suppose that: a = 4 b0011;// b = 4 b0100;// d = 6; e = 4; f = 2;//then,a + b //add a and b; evaluates to 4 b0111b - a //subtract a from b; evaluates to 4 b0001a * b //multiply a and b; evaluates to 4 b1100d / e //divide d by e, evaluates to 4 b0001. Truncates fractional parte ** f //raises e to the power f, evaluates to 4 b1111//power operator is most likely not synthesibleIf any operand bit has a value x , the result of the expression is all x.

2 If an operand is not fully known the result cannot be - OperatorsArithmetic Operators (cont.)Modulus operator yields the remainder from division of two numbersIt works like the modulus operator in CModulus is synthesible3 % 2; //evaluates to 116 % 4; //evaluates to 0-7 % 2; //evaluates to -1, takes sign of first operand7 % -2; //evaluates to 1, takes sign of first operandVerilog - OperatorsArithmetic Operators (cont.)IUnary operatorsIOperators + and - can act as unary operatorsIThey indicate the sign of an , -4 // negative four+5 // positive five!!! Negative numbers are represented as 2 s compliment numbers !!!!!! Use negative numbers only as type integer or real !!!!!! Avoid the use of<sss> <base> <number>in expressions !!!!!! These are converted to unsigned 2 s compliment numbers !

3 !!!!! This yields unexpected results in simulation and synthesis !!! Verilog - OperatorsArithmetic Operators (cont.)IThe logic gate realization depends on several variablesIcoding styleIsynthesis tool usedIsynthesis constraints (more later on this)ISo, when we say + , is it adderIlook-ahead-carry adder (how many bits of lookahead to be used?)Icarry-save adderWhen writing RTL code, keep in mind what will eventually be neededContinually thinking about structure, timing, size, powerVerilog - OperatorsArithmetic Operators (cont.)16-bit adder with loose constraints:set_max_delay 2 [get_ports sum*]max delay = , area = 472 = 85 gatesVerilog - OperatorsArithmetic Operators (cont.)16-bit adder with tighter constraints:set_max_delay [get_ports sum*]max delay = , area = 2038 = 368gatesVerilog - OperatorsLogical OperatorsIVerilog Logical OperatorsIlogical-and(&&) //binary operatorIlogical-or(||) //binary operatorIlogical-not(!)

4 //unary operator //suppose that: a = 3 and b = 0, (a && b) //evaluates to zero(b || a) //evaluates to one(!a) //evaluates to 0(!b) //evaluates to 1//with unknowns: a = 2 b0x; b = 2 b10;(a && b) // evaluates to x//with (a == 2) && (b == 3) //evaluates to 1 only if both comparisons are trueVerilog - OperatorsLogical Operators (.cont)ILogical Operators evaluate to a 1 bit valueI0 (false), 1 (true), or x (ambiguous)IOperands not equal to zero are equivalent to oneILogical Operators take variables or expressions as operatorsVerilog - OperatorsRelational Operators (.cont)Igreater-than (>)Iless-than (<)Igreater-than-or-equal-to (>=)Iless-than-or-equal-to (<=)Relational Operators return logical 1 if expression is true, 0 if false//let a = 4, b = 3, = 4 b1010, y = 4 b1101, z = 4 b1xxxa <= b //evaluates to logical zeroa > b //evaluates to logical oney >= x //evaluates to logical 1y < z //evaluates to x!

5 !! Note: These are expensive and slow Operators at gate level !!! Verilog - OperatorsEquality Operators - LT is big and slow//8-bit less than detector//if a is less than b, output is logic onemodule less8(input [7:0] a,b,output z);assign z = (a < b) ? 1 b1 : 1 b0;endmoduleResults from - OperatorsEquality OperatorsIlogical equality (== )Ilogical inequality (!= )Ilogical case equality (===)Ilogical case inequality (!==)Equality Operators return logical 1 if expression is true, else 0 Operands are compared bit by bitZero filling is done if operands are of unequal length (Warning!)Logical case inequality allows for checking of x and z valuesChecking for X and Z is most definitely non-synthesible! Verilog - OperatorsEquality Operators (cont.)//let a = 4, b = 3, = 4 b1010, y = 4 b1101,//z = 4 b1xxz, m = 4 b1xxz, n = 4 b1xxxa == b //evaluates to logical 0x !

6 = y //evaluates to logical 1x == z //evaluates to xz === m //evaluates to logical 1z === n //evaluates to logical 0m !== n //evaluates to logical 1 Verilog - OperatorsBitwise OperatorsInegation ( ), and(&), or(|), xor(^), xnor(^- , -^)IPerform bit-by-bit operation on two operands (except )IMismatched length operands are zero extendedIx and z treated the samebitwise AND bitwise OR bitwise XOR bitwise XNOR0 1 x 0 1 x 0 1 x 0 1 x0 0 0 0 0 0 1 x 0 0 1 x 0 1 0 x1 0 1 x 1 1 1 1 1 1 0 x 1 0 1 xx 0 x x x x 1 x x x x x x x x xbitwise negation result0 11 0x xVerilog - OperatorsBitwise Operators (cont.)ILogical Operators result in logical 1, 0 or xIBitwise Operators results in a bit-by-bit value//let x = 4 b1010, y = 4 b0000x | y //bitwise OR, result is 4 b1010x || y //logical OR, result is 1 Verilog - OperatorsBitwise Operators give bit-by-bit results//8-bit wide ANDmodule and8(input [7:0] a,b,output [7:0] z).

7 Assign z = a endmoduleU12U9U14U16U11U13U15U10z[5]b[1] z[6]b[0]a[7]z[7]a[6]a[5]a[4]a[3]b[2]a[2] b[3]b[4]b[5]a[0]b[6]a[1]b[7]z[0]z[1]z[2] z[3]z[4]z[7:0]a[7:0]b[7:0]a[7:0]b[7:0]z[ 7:0] Verilog - OperatorsReduction OperatorsIand(&), nand( &), or(|), nor( |) xor(^), xnor(^ , ^)IOperates on only one operandIPerforms a bitwise operation on all bits of the operandIReturns a 1-bit resultIWorks from right to left, bit by bit//let x = 4 b1010&x //equivalent to 1 & 0 & 1 & 0. Results in 1 b0|x //equivalent to 1 | 0 | 1 | 0. Results in 1 b1^x //equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1 b0A good example of the XOR operator is generation of parityVerilog - OperatorsReduction Operators //8-bit parity generator//output is one if odd # of onesmodule parity8(input [7:0] d_in,output parity_out);assign parity_out = ^d_in;endmoduleU7U10U9U8U6n5n6n8n7d_in[6 ]d_in[5]d_in[4]d_in[3]d_in[7]d_in[2]d_in [1]d_in[0]parity_outd_in[7:0]d_in[7:0]pa rity_outVerilog - OperatorsShift OperatorsIright shift (>>)Ileft shift (<<)Iarithmetic right shift (>>>)Iarithmetic left shift (<<<)IShift operator shifts a vector operand left or right by a specifiednumber of bits, filling vacant bit positions with do not wrap shift uses context to determine the fill let x = 4 b1100y = x >> 1; // y is 4 b0110y = x << 1; // y is 4 b1000y = x << 2.

8 // y is 4 b0000 Verilog - OperatorsArithmetic Shift OperatorsIarithmetic right shift (>>>)IShift right specified number of bits, fill with value of sign bit ifexpression is signed, othewise fill with left shift (<<<)IShift left specified number of bits, filling with - OperatorsConcatenation operator {,}IProvides a way to append busses or wires to make bussesIThe operands must be sizedIExpressed as operands in braces separated by commas//let a = 1 b1, b = 2 b00, c = 2 b10, d = 3 b110y = {b, c} // y is then 4 b0010y = {a, b, c, d, 3 b001} // y is then 11 b10010110001y = {a, b[0], c[1]} // y is then 3 b101 Verilog - OperatorsReplication operator { { } }IRepetitive concatenation of the same numberIOperands are number of repetitions, and the bus or wire//let a = 1 b1, b = 2 b00, c = 2 b10, d = 3 b110y = { 4{a} } // y = 4 b1111y = { 4{a}, 2{b} } // y = 8 b11110000y = { 4{a}, 2{b}, c } // y = 8 b1111000010 Verilog - OperatorsConditional operator ?

9 :IOperates like the C statementIconditionalexpression ? trueexpression : falseexpression ;IThe conditionalexpression is first evaluatedIIf the result is true, trueexpression is evaluatedIIf the result is false, falseexpression is evaluatedIIf the result is x:Iboth true and false expressions are evaluated,..Itheir results compared bit by bit,..Ireturns a value of x if bits differ, value of the bits if they are the is an ideal way to model a multiplexer or tri- State - OperatorsConditional operator (cont.)//8-bit wide, 2:1 muxmodule mux2_1_8wide(input sel,input [7:0] d_in1, d_in0,output [7:0] d_out);assign d_out = sel ? d_in1 : d_in0;endmoduleU16U12U13U14U15U11U10U17d _out[7]d_out[6]seld_out[4]d_out[2]d_in0[ 1]d_in0[2]d_out[0]d_in0[3]d_in1[7]d_in0[ 4]d_in0[5]d_in1[6]d_in0[6]d_in1[5]d_in1[ 4]d_in0[7]d_in1[3]d_in1[2]d_in1[1]d_in1[ 0]d_in0[0]d_out[7:0]d_in1[7:0]d_in0[7:0] d_in0[7:0]d_in1[7:0]seld_out[7:0] Verilog - OperatorsConditional operator (cont.)

10 //8-bit wide,//active-low enabled tri- State buffermodule ts_buff8(input [7:0] d_in,input en_n,output [7:0] d_out);assign d_out = ~en_n ? d_in : 8 bz;endmoduled_out_tri[4]U2d_out_tri[1]d_ out_tri[6]d_out_tri[3]d_out_tri[0]d_out_ tri[5]d_out_tri[2]d_out_tri[7]d_out[4]d_ out[5]d_in[7]d_out[6]d_in[6]d_out[7]d_in [5]d_in[4]d_in[3]d_in[2]d_in[1]d_in[0]n1 6en_nd_out[0]d_out[1]d_out[2]d_out[3]d_i n[7:0]d_out[7:0]en_nd_in[7:0]d_out[7:0]V erilog - OperatorsMore Lexical ConventionsIThe assign statement places a value (a binding) on a wireIAlso known as a continuous assignIA simple way to build combinatorial logicIConfusing for complex functionsIMust be used outside a procedural statement (always)//two input mux, output is z, inputs in1, in2, selassign z = (a | b);assign a = in1 assign b = in2 Verilog - OperatorsSome More Lexical ConventionsIThe order of execution of the assign statements is unknownIWe must fake parallel gates operate in parallelIThe assign statements fire when the RHS variables changeIRHS = a, b, in1, in2, selIThe values of a, b, and z are updated at the end of the timestepIIn the next time step if variables changed the next result is postedIThis repeats until no further changes time advances//two input mux, output is z, inputs in1, in2, selassign z = (a | b);assign a = in1 assign b = in2