Very low capacitance ESD protection

1 1162534I/O1I/O1 GNDVBUSI/O2I/O2 Functional diagram (top view)Features 2 data- line protection Protects VBUS Very low capacitance : pF max. Very low leakage current: 150 nA max. SOT-666 and SOT23-6L packages RoHS compliantBenefits Very low capacitance between lines to GND for optimized data integrity andspeed Low PCB space consumption: mm max for SOT-666 and 9 mm max forSOT23-6L Enhanced esd protection : IEC 61000-4-2 level 4 compliance guaranteed atdevice level, hence greater immunity at system level esd protection of VBUS High reliability offered by monolithic integration Low leakage current for longer operation of battery powered devices Fast response time Consistent D+ / D- signal balance: Very low capacitance matching tolerance I/O to GND = pF Compliant with USB requirementsComplies with the following standards: IEC 61000-4-2 level 4: 15 kV (air discharge) 8 kV (contact discharge)Applications USB ports up to 480 Mb/s (high speed) Compatible with USB low and full speed Ethernet port.

2 10/100 Mb/s SIM card protection Video line protection Portable electronicsDescriptionThe USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devicesdedicated to esd protection of high speed interfaces, such as USB , Ethernetlinks and video very low line capacitance secures a high level of signal integrity withoutcompromising in protecting sensitive chips against the most stringently characterizedESD status linkUSBLC6-2 Very low capacitance ESD protectionUSBLC6-2 DatasheetDS4260 - Rev 6 - October 2020 For further information contact your local STMicroelectronics sales 1. Absolute ratings (Tamb = 25 C)SymbolParameterValueUnitVPPPeak pulse voltageIEC 61000-4-2 level 4 standard:Air dischargeContact dischargeMIL STD883G-Method 3015-7151525kVTstgStorage temperature range-55 to +150 CTjOperating junction temperature range-40 to +125 CTLM aximum lead temperature for soldering during 10 s at 5 mm260 CTable 2.

3 Electrical characteristics (Tamb = 25 C)SymbolParameterTest currentVRM = V10150nAVBRB reakdown voltagebetweenVBUS and GNDIR = 1 mA6 VVFF orward voltageIF = 10 voltageIPP = 1 A, 8/20 sAny I/O pin to GND12 VIPP = 5 A, 8/20 sAny I/O pin to GND17Ci/o-GNDC apacitancebetween I/O andGNDVR = I/OVR = Ci/o- - Rev 6page 2 (curves)Figure 1. capacitance versus voltage (typical values) (pF)F=1 MHzV =30mVT=25 COSCRMSjC=I/O-I/OjC =I/O-GNDOData line voltage (V)Figure 2. line capacitance versus frequency (typicalvalues) (pF)V =30mVT=25 COSCRMSjV =0V to (MHz)Figure 3. Relative variation of leakage current versusjunction temperature (typical values)110100255075100125T ( C)jV =5 VBUSI [TRM j] / I [TRM j = 25 C]Figure 4. Frequency (dB)F(Hz)USBLC6-2 Characteristics (curves)DS4260 - Rev 6page 3/212 Technical protectionThe USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail clamping voltage VCL can be calculated as follow:VCL+ = VTRANSIL + VF for positive surgesVCL- = - VF for negative surgeswith: VF = VT + (VF forward drop voltage) / (VT forward drop threshold voltage)and VTRANSIL = VBR + exampleWe assume that the value of the dynamic resistance of the clamping diode is typically:Rd = and VT = VWe assume that the value of the dynamic resistance of the transil diode is typically:Rd_TRANSIL = and VBR = V For an IEC 61000-4-2 surge level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 ), VBUS = +5 V, and if in first approximation, we assume that:Ip = Vg / Rg = 24 , we find:VCL+ = + VVCL- = -13 VNote.

4 The calculations do not take into account phenomena due to parasitic protection application exampleIf we consider that the connections from the pin VBUS to VCC, from I/O to data line and from GND to PCB GNDplane are done by tracks of 10 mm long and mm large, we assume that the parasitic inductances LVBUS, LI/Oand LGND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line , due to the risetime of this spike (tr = 1 ns), the voltage VCL has an extra value equal to + dI/dt is calculated as:dI/dt = Ip/tr = 24 A/nsThe overvoltage due to the parasitic inductances is: = = 6 nH x 24 A/ns = 144 VBy taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage willbe:VCL+ = + + 144 + 144 = VVCL- = - 144 - 144 = VWe can significantly reduce this phenomena with simple layout optimization. It is for this reason that somerecommendations have to be followed (see ).

5 USBLC6-2 Technical informationDS4260 - Rev 6page 4/21 Figure 5. ESD behavior: parasitic phenomena due to unsuitable layoutVBUSLI/OLVBUSLGNDLI/OLGNDV pinCCVCLVFI/O pinVTRANSILV+ VTRANSIL F- VFVCL-t = 1 nsrttt = 1 nsrVCL+GND pinData linePositiveSurgeNegativeSurgeESD surge on data linedidtLI/O+ LGND didtdidt-LI/O- LGND didtdidtV+= V+ V + L+ Lsurge > 0 CLTRANSIL F I/OGNDV = -V - L- Lsurge > 0CL-F +=USBLC6-2 Surge protection application exampleDS4260 - Rev 6page 5 to ensure good ESD protectionWhile the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of theboard. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pinand from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena(see Figure 6. ESD behavior: layout optimization and Figure 5. ESD behavior: parasitic phenomena due tounsuitable layout for layout consideration).

6 Figure 6. ESD behavior: layout optimizationUnsuitable layoutOptimized layout11625341162534 Figure 7. ESD behavior: measurement conditions+5 VINOUTTEST BOARDESD SURGEUSBLC6-2SC6 Figure 8. ESD response to IEC 61000-4-2 (+15 kV airdischarge)Figure 9. ESD response to IEC 61000-4-2 (-15 kV airdischarge)Note:Important: A good precaution to take is to put the protection device as close as possible to the disturbancesource (generally the connector).USBLC6-2 How to ensure good ESD protectionDS4260 - Rev 6page 6 phenomenonFigure 10. Crosstalk phenomenonLine 1 line 2VG1VG2RG1RG2 DRIVERSRL1RL2 RECEIVERS +112VG1VG2 +221VG2VG1 The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor ( 12 or 21) increaseswhen the gap across lines decreases, particularly in silicon dice. In the above example the expected signal onload RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1.

7 This part of the VG1 signalrepresents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be takeninto account when the drivers impose fast digital data or high frequency analog signals in the disturbing line . Theperturbed line will be more affected if it works with low voltage signal or high load impedance (few k ).Figure 11. Analog crosstalk measurementsNETWORK ANALYSERPORT 2 NETWORK ANALYSERPORT 1 TEST BOARDVbusUSBLC6-2SC6 Figure 11. Analog crosstalk measurements shows the measurement circuit for the analog application. In usualfrequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (seeFigure 12. Analog crosstalk results).USBLC6-2 Crosstalk behaviorDS4260 - Rev 6page 7/21 Figure 12. Analog crosstalk (Hz)As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operatingsignals.

8 The frequency response (Figure 4. Frequency response) gives attenuation information and shows thatthe USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirablesignals like GSM (900 MHz) frequencies, for behaviorDS4260 - Rev 6page 8 examplesFigure 13. USB port application diagram using USBLC6-2 HUB-DOWNSTREAMTRANSCEIVER+ 5 VRSRSRSRSRPDRPDRPDRPDP rotectingBus SwitchDEVICE-UPSTREAMTRANSCEIVER+ +D-GNDVBUSVBUSVBUSRX LS/FS+RX LS/FS+RX LS/FS+RX LS/FS+RX HS+RX HS+RX HS+RX HS+TX HS+TX HS+TX HS+TX HS+TX LS/FS+TX LS/FS+TX LS/FS+TX LS/FS+RSRSUSB connectorTX LS/FS -TX LS/FS -TX LS/FS -TX LS/FS -RX LS/FS -RX LS/FS -RX LS/FS -RX LS/FS -RX HS -RX HS -RX HS -RX HS -TX HS -TX HS -TX HS -TX HS -GNDGNDGNDGNDSW2 DEVICE-UPSTREAMTRANSCEIVERUSBLC6-4SC6 USBLC6-2P6 USBLC6-2SC6+ +D-GNDRSRSUSB connectorSW2 OpenClosed then openHigh Speed HSOpenClosedFull Speed FSClosedOpenLow Speed LSSW2SW1 ModeUSBLC6-2 Application examplesDS4260 - Rev 6page 9/21 Figure 14.

9 T1/E1/Ethernet protectionDATATRANSCEIVERSMP75-8 SMP75-8 TxRx+VCC+ modelFigure 15. PSpice model shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined bythe PSpice parameters given in Figure 16. PSpice 15. PSpice modelMODEL = DlowMODEL = DhighVBUSLI/OLGNDGNDD+inMODEL = DzenerRI/OLI/OD-inRI/OLI/OLI/ORGNDRI/OD- outRI/OMODEL = DlowMODEL = DhighLI/OD+outRI/ONote:This simulation model is available only for an ambient temperature of 27 modelDS4260 - Rev 6page 10/21 Figure 16. PSpice 17. USBLC6-2 PCB layout considerationsD+inD+outD-outGNDUSBLC6-2D -inVBUS1C = 100nFBUSUSBLC6-2 PSpice modelDS4260 - Rev 6page 11/213 Package informationIn order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance. ECOPACK specifications, grade definitions and productstatus are available at: ECOPACK is an ST package informationFigure 18.

10 SOT23-6L package outlineA2 ALHcbEDeeA1 Table 3. SOT23-6L package mechanical (1) 1. Value in inches are converted from mm and rounded to 4 decimal digits USBLC6-2 Package informationDS4260 - Rev 6page 12/21 Figure 19. Footprint recommendations, dimensions in mm (inches) ( ) ( ) ( ) ( ) ( ) ( )USBLC6-2 SOT23-6L package informationDS4260 - Rev 6page 13 package informationFigure 20. SOT-666 package outlineDL1ebE1L2 EAA3 USBLC6-2 SOT-666 package informationDS4260 - Rev 6page 14/21 Table 4. SOT-666 package mechanical (1) 1. Value in inches are converted from mm and rounded to 4 decimal digits Figure 21. Footprint recommendations, dimensions in package informationDS4260 - Rev 6page 15 informationFigure 22. Marking layout (refer to ordering informationtable for marking)X X X XFigure 23. Package orientation in reelFigure 24. Tape and reel orientationFigure 25. Reel dimensions (mm)USBLC6-2 Packing informationDS4260 - Rev 6page 16/21 Figure 26.