Transcription of Set-Reset (SR) Latch
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Set-Reset (SR) Latch
C. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200 Set-Reset (SR) LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high inputs (only one can be active)cross-coupled Nand gatesactive low inputs (only one can be active)SRQ+Q+Function00 QQStorage State01 0 1 Reset10 1 0 Set110-?0-?Indeterminate StateSRQ+Q+Function001-?1-?Indeterminate State01 1 0 Set10 0 1 Reset11 QQStorage StateSRQQSRQQC. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200 Enabled Set-Reset (SR) LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high inputs (S & R cannot be active)cross-coupled Nand gatesactive low inputs (S & R cannot be active)ESRQ+Q+Function0xxQQStorage State100 QQStorage State101 0 1 Reset110 1 0 Set1110-?
To verify that a sequential logic circuit will work at the specified clock frequency, fclk, we must consider the clock period, Tp, the ... Asynchronous interfaces lead to metastability (minimize the async interface & double clock data to reduce probability of metastability)
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