12-Bit, 6 GSPS/10.25 GSPS, JESD204B, RF Analog-to-Digital ...

1 12-Bit, 6 gsps , JESD204B, RF Analog-to-Digital ConverterData Sheet AD9213 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, Box 9106, Norwood, MA 02062-9106, : 2020 Analog Devices, Inc.

2 All rights reserved. Technical Support FEATURES High instantaneous dynamic range NSD 155 dBFS/Hz at 10 gsps with 9 dBFS, 170 MHz input 153 dBFS/Hz at 10 gsps with 1 dBFS, 170 MHz input SFDR: 70 dBFS at 10 gsps with 1 dBFS, 1000 MHz input SFDR excluding H2 and H3 (worst other spur): 89 dBFS at 10 gsps with 1 dBFS, 1000 MHz input Low power dissipation: < W typical at 10 gsps Integrated input buffer ( GHz input bandwidth) V p-p full-scale analog input with RIN = 50 Overvoltage protection 16-lane JESD204B output (up to 16 Gbps line rate) Multichip synchronization capable with 1 sample accuracy DDC NCO synchronization included Integrated DDC Selectable decimation factors 16 profile settings for fast frequency hopping Fast overrange detection for efficient AGC On-chip temperature sensor On-chip negative voltage generators Low CER.

3 <1 10 16 12 mm 12 mm, 192-ball BGA-ED package GENERAL DESCRIPTION The AD9213 is a single, 12-bit, 6 gsps , radio frequency (RF) Analog-to-Digital converter (ADC) with a GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instan-taneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability. The AD9213 achieves dynamic range and linearity performance while consuming < W typical. The device is based on an inter-leaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor.

4 The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions. Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three.

5 For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count. The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of 20 C to +115 C. FUNCTIONAL BLOCK DIAGRAM VIN_PAVDD2( )AVNN1( )BUFFERAD9213 VIN_NVCMCLK_PCLK_NCLKVDD_LF( )FDAVDD( )JVDD2( )JVDD( )SERDOUTx[0]SERDOUTx[1]SERDOUTx[15]DVDD( )AGNDDGNDSYNCINB_xSYSREF_xTRIG_xSVDD2( )SDIOGPIO[0] TO GPIO[4]ADCCORE12Tx OUTPUTSSCLKCSB2 DIGITALGAINSIGNALMONITORCLOCKDISTRIBUTIO NJESD204 BSUBCLASS 1 CONTROLGPIOASSIGNMENTSPICONTROLDIGITALDO WNCONVERTER16I/Q16 JESD204 BSERIALIZER15030-001 DFORMAT Figure 1.

6 AD9213 Data Sheet Rev. A | Page 2 of 110 TABLE OF CONTENTS Features .. 1 General Description .. 1 Functional Block Diagram .. 1 Revision History .. 3 Specifications .. 4 AC Specifications .. 5 digital Specifications .. 6 Switching Specifications .. 7 Timing Specifications .. 8 Absolute Maximum Ratings .. 10 Thermal Characteristics .. 10 ESD Caution .. 10 Pin Configuration and Function Descriptions .. 11 Typical Performance Characteristics .. 14 AD9213-6G .. 14 AD9213-10G .. 20 Equivalent Circuits .. 27 Theory of Operation .. 30 ADC Architecture .. 30 Analog Input Considerations .. 30 Voltage Reference .. 31 Clock Input Considerations.

7 32 TMU .. 33 ADC Overrange and Fast Detect .. 34 ADC Overrange .. 34 Fast Threshold Detection (FD) .. 34 digital Downconverter (DDC) .. 35 DDC General Description .. 35 DDC Frequency Translation .. 37 DDC Decimation Filters .. 44 DDC Gain Stage .. 48 DDC Complex to Real Conversion .. 48 DDC Example Configurations .. 49 Signal Monitor .. 53 SPORT Over JESD204B .. 53 digital Outputs .. 56 Introduction to the JESD204B Interface .. 56 JESD204B Overview .. 56 Functional Overview .. 57 JESD204B Link Establishment .. 57 Physical Layer (Driver) Outputs .. 59 Setting Up the AD9213 digital Interface .. 60 Latency .. 63 End to End Total Latency.

8 63 Example Latency 63 LMFC Referenced Latency .. 63 Deterministic Latency .. 65 Subclass 0 Operation .. 65 Subclass 1 Operation .. 65 Multichip Synchronization (MCS) .. 67 Averaged SYSREF Mode For MCS .. 67 Sampled SYSREF Mode .. 67 MCS Averaged SYSREF Mode Setup .. 68 Test Modes .. 70 JESD204B Test Modes .. 70 Data Link Layer Test Modes .. 70 Serial Port Interface (SPI) .. 73 Configuration Using the SPI .. 73 SPI Accessible Features .. 73 Hardware Interface .. 73 Memory Map .. 74 Reading the Memory Map Register Tables .. 74 Applications Information .. 108 Startup Sequence .. 108 Changing Sample Clock Frequency Without Power Down 108 Power Supply Recommendations.

9 109 Outline Dimensions .. 110 Ordering Guide .. 110 Data Sheet AD9213 Rev. A | Page 3 of 110 REVISION HISTORY 3/2020 Rev. 0 to Rev. A Changes to Figure 1 .. 1 Changes to Power Supply Parameter, SVDD2, Table 1 .. 4 Changes to Table 3 .. 6 Changes to Table 8 .. 12 Changes to Figure 22 .. 16 Changes to Figure 53 and Figure 54 .. 22 Changes to Figure 83 .. 28 Change to Setting up the AD9213 digital Interface Section .. 60 Change to Setting Deterministic Latency Registers Section .. 66 Changes to Table 36 .. 74 Changes to Figure 126 ..109 8/2019 Revision 0: Initial Version AD9213 Data Sheet Rev. A | Page 4 of 110 SPECIFICATIONS Nominal supply voltages, specified maximum sampling rate, internal reference, analog input (AIN) = dBFS.

10 Minimum/maximum specifications represent performance at 20 C TJ +115 C, unless otherwise noted. Typical specifications represent performance at TJ = 70 C. Table 1. Parameter AD9213-6G AD9213-10G Unit Min Typ Max Min Typ Max RESOLUTION 12 12 Bits ACCURACY No Missing Codes Guaranteed Guaranteed Offset Error 10 +9 11 0 +11 LSB Gain Error + + %FSR Differential Nonlinearity (DNL) + + LSB Integral Nonlinearity (INL) + + LSB ANALOG INPUTS Differential Input Voltage Range (Internal VREF = V) V p-p Resistance (RIN) 50 Capacitance 1 1 pF Internal Common-Mode Voltage (VCM) V Analog Full Power Bandwidth (Internal Termination)