14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to ...

1 14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to -Digital Converter Data Sheet AD9695. FEATURES APPLICATIONS. JESD204B (Subclass 1) coded serial digital outputs Communications Lane rates up to 16 Gbps Diversity multiband, multimode digital receivers W total power at 1300 MSPS 3G/4G, TD-SCDMA, WCDMA, GSM, LTE. 800 mW per ADC channel General-purpose software radios SNR = dBFS at 172 MHz ( V p-p input range) Ultrawideband satellite receiver SFDR = 78 dBFS at MHz ( V p-p input range) Instrumentation Noise density Oscilloscopes dBFS/Hz ( V p-p input range) Spectrum analyzers dBFS/Hz ( V p-p input range) Network analyzers V, V, and V supply operation Integrated RF test solutions No missing codes Radars Internal ADC voltage reference Electronic support measures, electronic counter measures, Flexible input range and electronic counter-counter measures V p-p to V p-p ( V p-p typical)

2 High speed data acquisition systems 2 GHz usable analog input full power bandwidth DOCSIS CMTS upstream receive paths >95 dB channel isolation/crosstalk Hybrid fiber coaxial digital reverse path receivers Amplitude detect bits for efficient AGC implementation Wideband digital predistortion 2 integrated digital downconverters per ADC channel 48-bit NCO. Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4. Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity FUNCTIONAL BLOCK DIAGRAM. AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD.

3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ). BUFFER. VIN+A ADC 14. VIN A CORE. PROGRAMMABLE. CROSSBAR MUX. CROSSBAR MUX. DIGITAL DOWN- FIR FILTER. CONVERTER. JESD204B SERDOUT0 . FAST SIGNAL LINK 4. SERDOUT1 . DETECT MONITOR AND. Tx SERDOUT2 . DIGITAL DOWN- OUTPUTS SERDOUT3 . CONVERTER. VIN+B ADC 14. VIN B CORE. BUFFER. VREF. SYNCINB . PDWN/STBY. JESD204B CLOCK. SYSREF SUBCLASS 1 DISTRIBUTION. CONTROL FD_A/GPIO_A0. CLK+ GPIO MUX. SPI AND. CONTROL FD_B/GPIO_B0. REGISTERS. CLK 2. 4 AD9695. 15660-001. AGND SDIO SCLK CSB DRGND DGND. Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable.

4 However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, Box 9106, Norwood, MA 02062-9106, No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 2017 2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support AD9695 Data Sheet TABLE OF CONTENTS. Features .. 1 DDC General Description.

5 42. Applications .. 1 DDC Frequency Translation .. 45. Functional Block Diagram .. 1 DDC Decimation Filters .. 53. Revision History .. 3 DDC Gain Stage .. 60. General Description .. 4 DDC Complex to Real Conversion .. 61. Product Highlights .. 4 DDC Mixed Decimation Settings .. 62. Specifications .. 5 DDC Example Configurations .. 64. DC Specifications .. 5 DDC power Consumption .. 67. AC Specifications 1300 MSPS .. 6 Signal Monitor .. 68. AC Specifications 625 MSPS .. 8 SPORT Over JESD204B .. 69. Digital Specifications .. 9 Digital Outputs .. 71. Switching Specifications .. 10 Introduction to the JESD204B Interface.

6 71. Timing Specifications .. 11 JESD204B Overview .. 71. Absolute Maximum Ratings .. 13 Functional Overview .. 72. Thermal Characteristics .. 13 JESD204B Link Establishment .. 72. ESD 13 Physical Layer (Driver) Outputs .. 74. Pin Configuration and Function Descriptions .. 14 Setting Up the AD9695 Digital Interface .. 75. Typical Performance Characteristics .. 16 Deterministic 81. 1300 MSPS .. 16 Subclass 0 Operation .. 81. 625 MSPS .. 21 Subclass 1 Operation .. 81. Equivalent Circuits .. 25 Multichip Synchronization .. 83. Theory of Operation .. 27 Normal Mode .. 83. ADC Architecture .. 27 Timestamp Mode.

7 83. Analog Input Considerations .. 27 SYSREF 85. Voltage 30 SYSREF Setup/Hold Window 87. DC Offset Calibration .. 30 Latency .. 89. Clock Input 30 End to End Total Latency .. 89. power -Down/Standby Mode .. 33 Example Latency Calculations .. 89. Temperature Diode .. 33 LMFC Referenced Latency .. 89. ADC Overrange and Fast 34 Test Modes .. 91. ADC Overrange .. 34 ADC Test Modes .. 91. Fast Threshold Detection (FD_A and FD_B) .. 34 JESD204B Block Test Modes .. 92. ADC Application Modes and JESD204B Tx Converter Serial Port Interface (SPI) .. 94. Mapping .. 35 Configuration Using the SPI .. 94. Programmable Finite Impulse Response (FIR) 37 Hardware Interface.

8 94. Supported Modes .. 37 SPI Accessible Features .. 94. Programming Instructions .. 39 Memory Map .. 95. Digital Downconverter (DDC).. 42 Reading the Memory Map Register Table .. 95. DDC I/Q Input Selection .. 42 Memory Map Registers .. 96. DDC I/Q Output Selection .. 42 Applications Information .. 134. Rev. C | Page 2 of 136. Data Sheet AD9695. power Supply Recommendations .. 134 Outline Dimensions ..136. Layout GuideLines .. 135 Ordering Guide ..136. AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) .. 135. REVISION HISTORY. 6/2020 Rev. B to Rev. C 10/2017 Rev. 0 to Rev. A. Changes to Table 48 ..97 Changes to Table 5.

9 10. Change to Theory of Operation Section .. 27. 12/2019 Rev. A to Rev. B Changes to Table Changes to Input Common Mode Updated Outline Dimensions ..135. Added DDC power Consumption Section and Table 31;. Renumbered Sequentially ..67 9/2017 Revision 0: Initial Version Changes to Table 35 ..76. Changes to Table 36 ..77. Changes to Table 37 ..78. Changes to Table 48 ..96. Rev. C | Page 3 of 136. AD9695 Data Sheet GENERAL DESCRIPTION. The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS Analog-to - monitoring capability. The signal monitoring block provides digital converter (ADC). The device has an on-chip buffer and a additional information about the signal being digitized by the sample-and-hold circuit designed for low power , small size, and ADC.

10 Ease of use. This product is designed to support communications The user can configure the Subclasss 1 JESD204B-based high applications capable of direct sampling wide bandwidth analog speed serialized output using either one lane, two lanes, or four signals of up to 2 GHz. The 3 dB bandwidth of the ADC input lanes, depending on the DDC configuration and the acceptable is 2 GHz. The AD9695 is optimized for wide input bandwidth, lane rate of the receiving logic device. Multidevice synchronization high sampling rate, excellent linearity, and low power in a small is supported through the SYSREF and SYNCINB input pins.