8-bit serial-in, serial or parallel-out shift register ...

1 74HC595; 74 HCT595. 8-bit serial -in, serial or parallel-out shift register with output latches ; 3-state Rev. 11 10 September 2021 Product data sheet 1. General description The 74HC595; 74 HCT595 is an 8-bit serial -in/ serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register . Data is shifted on the LOW-to-HIGH.

2 Transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register . Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

3 2. Features and benefits Wide supply voltage range from to V. CMOS low power dissipation High noise immunity 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs shift register with direct clear 100 MHz (typical) shift out frequency Latch-up performance exceeds 100 mA per JESD 78 Class II Level B. Complies with JEDEC standards: JESD8C ( V to V). JESD7A ( V to V). Input levels: For 74HC595: CMOS level For 74 HCT595: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V. MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C.

4 3. Applications serial -to-parallel data conversion Remote control holding register Nexperia 74HC595; 74 HCT595. 8-bit serial -in, serial or parallel-out shift register with output latches ; 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC595D -40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1. 74 HCT595D body width mm 74HC595PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1. 74 HCT595PW body width mm 74HC595BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1.

5 74 HCT595BQ very thin quad flat package; no leads; 16 terminals;. body mm 74HC595BZ -40 C to +125 C DHXQFN16 plastic, leadless dual in-line compatible thermal SOT8016-1. enhanced extreme thin quad flat package;. no leads; 16 terminals; mm pitch;. body 2 mm mm mm 5. Functional diagram 14 DS. 11 SHCP. 8-STAGE shift register . 10 MR. Q7S 9. 12 STCP. 8-bit STORAGE register . 13 OE. 3-STATE OUTPUTS. Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7. 15 1 2 3 4 5 6 7 mna554. Fig. 1. Functional diagram 13. EN3. 12. 11 12 C2. 10. SHCP STCP R SRG8. 9 11. Q7S C1/. 15. Q0 14 15.

6 1 1D 2D 3. Q1 1. 2. Q2 2. 14 3. DS Q3 3. 4. Q4 4. 5. Q5 5. 6. Q6 6. 7. Q7 7. MR OE 9. 10 13. mna552 mna553. Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC_HCT595 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reserved Product data sheet Rev. 11 10 September 2021 2 / 21. Nexperia 74HC595; 74 HCT595. 8-bit serial -in, serial or parallel-out shift register with output latches ; 3-state STAGE 0 STAGES 1 TO 6 STAGE 7. DS D Q D Q D Q Q7S. FF0 FF7. CP CP. R R. SHCP. MR. D Q D Q. LATCH LATCH. CP CP.

7 STCP. OE. mna555. Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7. Fig. 4. Logic diagram 6. Pinning information Pinning 74HC595. 74 HCT595. 16 VCC. terminal 1. Q1. index area 1. Q2 2 15 Q0. Q3 3 14 DS. 74HC595. 74 HCT595 Q4 4 13 OE. Q5 5 12 STCP. Q1 1 16 VCC. Q6 6 GND(1) 11 SHCP. Q2 2 15 Q0. Q7 7 10 MR. Q3 3 14 DS. 8. 9. Q4 4 13 OE. GND. Q7S. Q5 5 12 STCP 001aao243. Q6 6 11 SHCP. Transparent top view Q7 7 10 MR. (1) This is not a ground pin. There is no electrical or GND 8 9 Q7S. mechanical requirement to solder the pad. In case 001aao242 soldered, the solder land should remain floating or connected to GND.

8 Fig. 5. Pin configuration for SOT109-1 (SO16) and SOT403-1 (TSSOP16) Fig. 6. Pin configuration for SOT763-1 (DHVQFN16). 74HC_HCT595 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reserved Product data sheet Rev. 11 10 September 2021 3 / 21. Nexperia 74HC595; 74 HCT595. 8-bit serial -in, serial or parallel-out shift register with output latches ; 3-state 74HC595. terminal 1. 16 VCC. Q1. index area Q2 2 15 Q0. 1. Q3 3 14 DS. Q4 4 13 OE. Q5 5 12 STCP. Q6 6 GND(1) 11 SHCP. Q7 7 10 MR. 8. 9. Q7S.

9 GND. aaa-032839. Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 7. Pin configuration SOT8016-1 (DHXQFN16). Pin description Table 2. Pin description Symbol Pin Description Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V). Q7S 9 serial data output MR 10 master reset (active LOW). SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW).

10 DS 14 serial data input Q0 15 parallel data output 0. VCC 16 supply voltage 74HC_HCT595 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reserved Product data sheet Rev. 11 10 September 2021 4 / 21. Nexperia 74HC595; 74 HCT595. 8-bit serial -in, serial or parallel-out shift register with output latches ; 3-state 7. Functional description Table 3. Function table H = HIGH voltage state; L = LOW voltage state; = LOW-to-HIGH transition;. X = don't care; NC = no change; Z = high-impedance OFF-state.