Four ADC, Two DAC, Low Power Codec with Audio DSPs Data ...

1 Four ADC, Two DAC, Low Power Codec with Audio DSPs Data Sheet ADAU1787 Rev. A Document Feedback Information furnished by analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, Box 9106, Norwood, MA 02062-9106, : 2019-2020 analog Devices, Inc. All rights reserved. Te c h n i c a l S u p p o r t FEATURES Programmable FastDSP Audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing 28-bit SigmaDSP Audio processing core Visually programmable using SigmaStudio Up to 50 MIPS performance Low latency, 24-bit ADCs and DACs 96 dB SNR (signal through PGA and ADC with A-weighted filter) 105 dB combined SNR (signal through DAC and headphone with A-weighted filter) Serial port fSYNC frequency from 8 kHz to 768 kHz 5 s group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions)

2 4 single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs 2 analog differential Audio outputs, configurable as either line output or headphone driver PLL supporting any input clock rate from 30 kHz to 27 MHz Full-duplex, 4-channel ASRCs 2, 16-channel serial Audio ports supporting I2S, left justified, or up to TDM16 8 interpolators and 8 decimators with flexible routing Power supplies analog AVDD at V typical Digital I/O IOVDD at V to V Digital DVDD at V typical Low Power ( mW for typical stereo ANC settings) I2C and SPI control interfaces, self boot from I2C EEPROM Flexible GPIO 42-ball, mm pitch, mm mm WLCSP APPLICATIONS Noise cancelling handsets, headsets, and headphones Bluetooth ANC handsets, headsets, and headphones Personal navigation devices Digital still and video cameras Musical instrument effect processors Multimedia speaker systems Smartphones GENERAL DESCRIPTION The ADAU1787 is a Codec with four inputs and two outputs that incorporates two digital signal processors (DSPs).

3 The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise cancelling headsets. With the addition of just a few passive components, the ADAU1787 provides a complete headset solution. Note that throughout this data sheet, multifunction pins, such as BCLK_0/MP1, are referred to either by the entire pin name or by a single function of the pin, for example, BCLK_0, when only that function is relevant. ADAU1787 Data SheetRev. A | Page 2 of 280 TABLE OF CONTENTS Features .. 1 Applications .. 1 General Description .. 1 Revision History .. 5 Functional Block Diagram .. 6 Specifications .. 7 analog Performance Specifications .. 7 Crystal Amplifier Specifications .. 9 Digital Input and Output Specifications .. 9 Power Supply 10 Power -Down Current .. 10 Typical Power Consumption .. 10 Digital Filters .. 11 Digital Timing Specifications .. 12 Absolute Maximum Ratings .. 16 Thermal Resistance .. 16 ESD Caution.

4 16 Pin Configuration and Function Descriptions .. 17 Typical Performance Characteristics .. 20 System Block Diagram .. 27 Theory of Operation .. 28 System Clocking and Power -Up .. 29 Power -Down Operation and Options .. 29 Example ADC to DAC Power -up .. 30 DVDD LDO Regulator .. 30 Clock Initialization .. 30 PLL .. 31 Multichip Phase Synchronization .. 32 Clock Output .. 32 Power Supply Sequencing .. 32 Signal Routing .. 33 Input Signal Paths .. 34 analog Inputs .. 34 Digital Microphone Inputs .. 35 ADCs .. 36 Output Signal Paths .. 37 analog 37 DACs .. 37 PDM Outputs .. 38 ASRCs .. 38 Interpolation and Decimation Blocks .. 39 Signal Levels .. 39 FastDSP Core .. 40 Instructions .. 40 Filter Precision .. 40 Flags and Conditional Execution .. 40 Input Sources .. 40 Power and Run Control .. 41 Data Memory .. 41 Parameters .. 41 Parameter Bank Switching .. 41 Parameter Bank Copying .. 41 Parameter Memory 42 FastDSP Parameter Safeload .. 42 SigmaDSP Core.

5 43 Read/Write Data Formats .. 44 Software Safeload .. 45 FastDSP Safeload .. 45 Program RAM, Parameter RAM, and Data RAM .. 46 Program RAM .. 46 Parameter RAM .. 46 Data RAM .. 46 Power Saving Options .. 47 Control Port .. 49 Burst Mode Communication .. 49 Reading and Writing to Memories .. 50 I2C Port .. 50 SPI Port .. 53 Self Boot .. 54 Multipurpose Pins .. 56 Serial Data Ports .. 57 Applications Information .. 59 Power Supply Bypass Capacitors .. 59 Layout .. 59 Grounding .. 59 PCB Stackup .. 59 Register Summary .. 60 Register Details .. 67 ADI Vendor ID Register .. 67 Device ID Registers .. 67 Data Sheet ADAU1787 Rev. A | Page 3 of 280 Revision Code Register .. 67 ADC, DAC, Headphone Power Controls Register .. 68 PLL, Microphone Bias, and PGA Power Controls Register .. 69 Digital Microphone Power Controls Register .. 70 Serial Port, PDM Output, and Digital Microphone CLK Power Controls Register .. 71 DSP Power Controls Register .. 72 ASRC Power Controls Register.

6 72 Interpolator Power Controls Register .. 73 Decimator Power Controls Register .. 74 State Retention Controls Register .. 75 Chip Power Control Register .. 76 Clock Control Register .. 77 PLL Input Divider Register .. 78 PLL Feedback Integer Divider (LSBs Register) .. 78 PLL Feedback Integer Divider (MSBs Register) .. 78 PLL Fractional Numerator Value (LSBs Register) .. 78 PLL Fractional Numerator Value (MSBs Register) .. 79 PLL Fractional Denominator (LSBs Register) .. 79 PLL Fractional Denominator (MSBs Register) .. 79 PLL Update Register .. 79 ADC Sample Rate Control Register .. 80 ADC IBIAS Controls Register .. 81 ADC HPF Control Register .. 81 ADC Mute and Compensation Control Register .. 82 analog Input Precharge Time Register .. 83 ADC Channel Mutes Register .. 84 ADC Channel 0 Volume Control Register .. 85 ADC Channel 1 Volume Control Register .. 86 ADC Channel 2 Volume Control Register .. 87 ADC Channel 3 Volume Control Register .. 88 PGA Channel 0 Gain Control MSBs, Mute, Boost, Slew Register.

7 89 PGA Channel 0 Gain Control LSBs Register .. 89 PGA Channel 1 Gain Control MSBs, Mute, Boost, Slew Register .. 90 PGA Channel 1 Gain Control LSBs Register .. 90 PGA Channel 2 Gain Control MSBs, Mute, Boost, Slew Register .. 91 PGA Channel 2 Gain Control LSBs Register .. 91 PGA Channel 3 Gain Control MSBs, Mute, Boost, Slew Register .. 92 PGA Channel 3 Gain Control LSBs Register .. 92 PGA Slew Rate and Gain Link Register .. 93 Microphone Bias Level and Current Register .. 93 Digital Microphone Clock Rate Control Register .. 94 Digital Microphone Channel 0 and Channel 1 Rate, Order, Mapping, and Edge Control Register .. 95 Digital Microphone Channel 2 and Channel 3 Rate, Order, Mapping, and Edge Control Register .. 96 Digital Microphone Channel 4 and Channel 5 Rate, Order, Mapping, and Edge Control Register .. 97 Digital Microphone Channel 6 and Channel 7 Rate, Order, Mapping, and Edge Control Register .. 98 Digtial Microphone Volume Options Register .. 99 Digital Microphone Channel Mute Controls Register.

8 100 Digital Microphone Channel 0 Volume Control Register .. 101 Digital Microphone Channel 1 Volume Control Register .. 102 Digital Microphone Channel 2 Volume Control Register .. 103 Digital Microphone Channel 3 Volume Control Register .. 104 Digital Microphone Channel 4 Volume Control Register .. 105 Digital Microphone Channel 5 Volume Control Register .. 106 Digital Microphone Channel 6 Volume Control Register .. 107 Digital Microphone Channel 7 Volume Control Register .. 108 DAC Sample Rate, Filtering, and Power Controls Register .. 109 DAC Volume Link, High-Pass Filter (HPF), and Mute Controls Register .. 110 DAC Channel 0 Volume Register .. 111 DAC Channel 1 Volume Register .. 112 DAC Channel 0 Routing Register .. 113 DAC Channel 1 Routing Register .. 115 Headphone Control Register .. 117 Fast to Slow Decimator Sample Rates Channel 0 and Channel 1 Register .. 117 Fast to Slow Decimator Sample Rates Channel 2 and Channel 3 Register .. 118 Fast to Slow Decimator Sample Rates Channel 4 and Channel 5 Register.

9 119 Fast to Slow Decimator Sample Rates Channel 6 and Channel 7 Register .. 120 Fast to Slow Decimator Channel 0 Input Routing Register .. 121 Fast to Slow Decimator Channel 1 Input Routing Register .. 122 Fast to Slow Decimator Channel 2 Input Routing Register .. 124 Fast to Slow Decimator Channel 3 Input Routing Register .. 125 Fast to Slow Decimator Channel 4 Input Routing Register .. 127 ADAU1787 Data SheetRev. A | Page 4 of 280 Fast to Slow Decimator Channel 5 Input Routing Register .. 128 Fast to Slow Decimator Channel 6 Input Routing Register .. 130 Fast to Slow Decimator Channel 7 Input Routing Register .. 131 Slow to Fast Interpolator Sample Rates Channel 0 and Channel 1 Register .. 133 Slow to Fast Interpolator Sample Rates Channel 2 and Channel 3 Register .. 134 Slow to Fast Interpolator Sample Rates Channel 4 and Channel 5 Register .. 135 Slow to Fast Interpolator Sample Rates Channel 6 and Channel 7 Register .. 136 Slow to Fast Interpolator Channel 0 Input Routing Register.

10 137 Slow to Fast Interpolator Channel 1 Input Routing Register .. 139 Slow to Fast Interpolator Channel 2 Input Routing Register .. 141 Slow to Fast Interpolator Channel 3 Input Routing Register .. 143 Slow to Fast Interpolator Channel 4 Input Routing Register .. 145 Slow to Fast Interpolator Channel 5 Input Routing Register .. 147 Slow to Fast Interpolator Channel 6 Input Routing Register .. 149 Slow to Fast Interpolator Channel 7 Input Routing Register .. 151 Input ASRC Control, Source, and Rate Selection Register . 153 Input ASRC Channel 0 and Channel 1 Input Routing Register .. 154 Input ASRC Channel 2 and Channel 3 Input Routing Register .. 155 Output ASRC Control Register .. 156 Output ASRC Channel 0 Input Routing Register .. 157 Output ASRC Channel 1 Input Routing Register .. 158 Output ASRC Channel 2 Input Routing Register .. 160 Output ASRC Channel 3 Input Routing Register .. 161 FastDSP Run Register .. 163 FastDSP Current Bank and Bank Ramping Controls Register.