14-Bit, 500 MSPS, JESD204B, Quad Analog-to-Digital ...

1 14-Bit, 500 MSPS, JESD204B, Quad Analog-to-Digital Converter Data Sheet AD9694. FEATURES Amplitude detect bits for efficient AGC implementation JESD204B (Subclass 1) coded serial digital outputs 4 integrated wideband digital processors Lane rates up to 15 Gbps 48-bit NCO, up to 4 cascaded half-band filters W total power at 500 MSPS Differential clock input 415 mW per ADC channel Integer clock divide by 1, 2, 4, or 8. SFDR = 82 dBFS at 305 MHz ( V p-p input range)S On-chip temperature diode SNR = dBFS at 305 MHz ( V p-p input range) Flexible JESD204B lane configurations Noise density = dBFS/Hz ( V p-p input range) APPLICATIONS. V, V, and V dc supply operation Communications No missing codes Diversity multiband, multimode digital receivers Internal ADC voltage reference 3G/4G, W-CDMA, GSM, LTE, LTE-A. analog input buffer General-purpose software radios On-chip dithering to improve small signal linearity Ultrawideband satellite receivers Flexible differential input range Instrumentation V p-p to V p-p ( V p-p nominal).

2 Radars GHz analog input full power bandwidth Signals intelligence (SIGINT). FUNCTIONAL BLOCK DIAGRAM. AVDD1 AVDD1_SR AVDD2 AVDD3 DVDD DRVDD1 DRVDD2 SPIVDD. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ). BUFFER 14 digital DOWN. VIN+A ADC CONVERTER. CORE (DDC). VIN A. VCM_AB 2. JESD204B Tx SERDOUTAB0 . FD_A HIGH SPEED OUTPUTS. FAST SIGNAL SERIALIZER SERDOUTAB1 . DETECT MONITOR. FD_B. BUFFER 14 digital DOWN. VIN+B ADC CONVERTER. CORE (DDC). VIN B. SIGNAL. MONITOR. AND FAST. DETECT. JESD204B SYSREF . CLOCK. CLK+ GENERATION SUBCLASS 1 SYNCINB AB. CONTROL. SYNCINB CD. CLK 2. 4. 8. BUFFER 14 digital DOWN- VIN+C ADC CONVERTER. CORE (DDC). VIN C. VCM_CD/VREF 2. JESD204B Tx SERDOUTCD0 . FD_C FAST SIGNAL HIGH SPEED OUTPUTS. SERIALIZER SERDOUTCD1 . DETECT MONITOR. FD_D. BUFFER 14 digital DOWN- VIN+D ADC CONVERTER. CORE (DDC). VIN D. SPI CONTROL PDWN/STBY. AD9694. 14808-001. AGND_SR AGND DRGND SDIO SCLK CSB. Figure 1. Rev. B Document Feedback Information furnished by analog Devices is believed to be accurate and reliable.

3 However, no responsibility is assumed by analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog Devices. Tel: 2016 2018 analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support AD9694 Data Sheet TABLE OF CONTENTS. Features .. 1 Half-Band Filters .. 43. Applications .. 1 DDC Gain Stage .. 44. Functional Block Diagram .. 1 DDC Complex to Real Conversion .. 44. Revision History .. 3 DDC Example Configurations .. 45. General Description .. 4 digital Outputs .. 50. Product Highlights .. 4 Introduction to the JESD204B Interface .. 50. 5 Setting Up the AD9694 digital Interface .. 50. DC Specifications .. 5 Functional Overview.

4 52. AC 6 JESD204B Link Establishment .. 52. digital Specifications .. 9 Physical Layer (Driver) Outputs .. 53. Switching Specifications .. 10 JESD204B Tx Converter Mapping .. 54. Timing Specifications .. 11 Configuring the JESD204B Link .. 56. Absolute Maximum 12 Latency .. 60. Thermal Resistance .. 12 End to End Total Latency .. 60. ESD Caution .. 12 Example Latency 60. Pin Configuration and Function Descriptions .. 13 LMFC referenced Latency .. 60. Typical Performance Characteristics .. 15 Deterministic 61. Equivalent Circuits .. 22 Subclass 0 61. Theory of Operation .. 24 Subclass 1 61. ADC Architecture .. 24 Multichip 63. analog Input 24 Normal 63. Voltage Reference .. 25 Timestamp Mode .. 63. DC Offset Calibration .. 26 SYSREF Input .. 65. Clock Input Considerations .. 26 SYSREF Setup/Hold Window Monitor .. 66. ADC Overrange and Fast 29 Test Modes .. 68. ADC Overrange .. 29 ADC Test Modes .. 68. Fast Threshold Detection (FD_A, FD_B, FD_C, and JESD204B Block Test Modes.)

5 69. FD_D) .. 29 Serial Port Interface .. 71. Signal Monitor .. 30 Configuration Using the SPI .. 71. SPORT Over JESD204B .. 30 Hardware 71. digital Downconverter (DDC) .. 33 SPI Accessible Features .. 71. DDC I/Q Input Selection .. 33 Memory Map .. 72. DDC I/Q Output Selection .. 33 Reading the Memory Map Register 72. DDC General Description .. 33 Memory Map Register Table Details .. 73. Frequency Translation .. 39 Applications Information .. 95. 39 Power Supply 95. DDC NCO and Mixer Loss and SFDR .. 40 Exposed Pad Thermal Heat Slug Recommendations .. 95. Numerically Controlled 40 AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) .. 95. FIR Filters .. 42 Outline Dimensions .. 96. 42 Ordering Guide .. 96. Rev. B | Page 2 of 96. Data Sheet AD9694. REVISION HISTORY. 2/2018 Rev. A to Rev. B Changes to Overview 42. Changed Document Title from Dual 14-Bit, GSPS, V/ Change to Phase-Locked Loop (PLL) Section .. 54. V Analog-to-Digital Converter to 14-Bit, 500 MSPS, Change to Table 26.

6 56. JESD204B Analog-to-Digital Converter .. Universal Changes to Table 27 .. 57. Change to Table 10 ..14 Changes to Example 2: ADC with DDC Option (Two ADCs Moved Temperature Diode Section ..28 Plus Two DDCs in Each Pair Section and Figure 92 .. 58. Added Example Latency Calculations Section, Example 12/2017 Rev. 0 to Rev. A Configuration 1 Section, Example Configuration 2 Section, Changed V p-p to V p-p .. Throughout Table 29, and Table 30; Renumbered Sequentially .. 60. Changes to Figure 1 Added Deterministic Latency Section, Subclass 0 Operation Changes to Endnote 3, Table 2 .. 7 Section, Subclass 1 Operation Section, Deterministic Latency Changes to Logic Outputs (FD_A, FD_B, FD_C, FD_D) Requirements Section, Setting Deterministic Latency Registers Parameter and digital OUTPUTS (SERDOUTABx / Section, and Figure 94; Renumbered Sequentially .. 61. SERDOUTCDx , x = 0 OR 1) Parameter, Table 5 .. 9 Added Figure 95 and Figure 96 .. 62. Changes to Output Parameter and Wake-Up Time Parameter, Added Multichip Synchronization Section, Normal Mode Table 6.)

7 10 Section, Timestamp Mode Section, Figure 63. Changes to Table 9 ..12 Added Figure 98 .. 64. Changes to Table 10 ..13 Added SYSREF Input Section, SYSREF Control Features Changes to Figure 18, Figure 19, Figure 20, and Figure 23 ..17 Section, Figure 99, Figure 100, Figure 101, and Figure 102 .. 65. Changes to Figure 47 and Figure 48 ..22 Changes to SYSREF Setup/Hold Window Monitor Section .. 66. Changes to analog Input Considerations Section and Changes to ADC Test Modes Section .. 68. Differential Input Configurations Section ..24 Deleted Register Table Summary Section and Table 38;. Changes to Table 11 ..25 Renumbered Sequentially .. 69. Changes to Voltage Reference Section, DC Offset Calibration Changes to Reading the Memory Map Register Table 72. Section, and Figure 62 ..26 Changes to Table 39 .. 73. Changes to Clock Duty Cycle Considerations Section and Changes to Power Supply Recommendations Section and Figure 65 ..27 Figure 106 .. 95. Added Input Clock Detect Section.

8 27. Changes to Temperature Diode 10/2016 Revision 0: Initial Version Changed General Description Section to Overview Section ..39. Rev. B | Page 3 of 96. AD9694 Data Sheet GENERAL DESCRIPTION Users can configure each pair of intermediate frequency (IF). The AD9694 is a quad, 14-bit, 500 MSPS Analog-to-Digital receiver outputs onto either one or two lanes of Subclass 1. converter (ADC). The device has an on-chip buffer and a JESD204B-based high speed serialized outputs, depending on sample-and-hold circuit designed for low power, small size, and the decimation ratio and the acceptable lane rate of the receiving ease of use. This device is designed for sampling wide bandwidth logic device. Multiple device synchronization is supported through analog signals of up to GHz. The AD9694 is optimized for the SYSREF , SYNCINB AB, and SYNCINB CD input pins. wide input bandwidth, high sampling rate, excellent linearity, The AD9694 has flexible power-down options that allow significant and low power in a small package.

9 Power savings when desired. All of these features can be pro- The quad ADC cores feature a multistage, differential pipelined grammed using the V capable, 3-wire SPI. architecture with integrated output error correction logic. Each The AD9694 is available in a Pb-free, 72-lead LFCSP and is ADC features wide bandwidth inputs supporting a variety of specified over the 40 C to +105 C junction temperature range. user-selectable input ranges. An integrated voltage reference This product may be protected by one or more or eases design considerations. international patents. The analog inputs and clock signals are differential inputs. Each PRODUCT HIGHLIGHTS. pair of ADC data outputs is internally connected to two DDCs 1. Low power consumption per channel. through a crossbar mux. Each DDC consists of up to five cascaded 2. JESD204B lane rate support up to 15 Gbps. signal processing stages: a 48-bit frequency translator, NCO, 3. Wide full power bandwidth supports IF sampling of signals and up to four half-band decimation filters.

10 Up to GHz. In addition to the DDC blocks, the AD9694 has several 4. Buffered inputs ease filter design and implementation. functions that simplify the automatic gain control (AGC) 5. Four integrated wideband decimation filters and numerically function in the communications receiver. The programmable controlled oscillator (NCO) blocks supporting multiband threshold detector allows monitoring of the incoming signal receivers. power using the fast detect output bits of the ADC. If the input 6. Programmable fast overrange detection. signal level exceeds the programmable threshold, the fast detect 7. On-chip temperature diode for system thermal management. indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Rev. B | Page 4 of 96. Data Sheet AD9694. SPECIFICATIONS. DC SPECIFICATIONS. AVDD1 = V, AVDD1_SR = V, AVDD2 = V, AVDD3 = V, DVDD = V, DRVDD1 = V, DRVDD2 = V, SPIVDD = V, 500 MSPS, clock divider = 4, V p-p full-scale differential input, V internal reference, AIN = dBFS, default SPI settings, unless otherwise noted.