LTC2508-32: 32-Bit Oversampling ADC with Configurable ...

1 LTC2508-321250832fcFor more information APPLICATION FEATURESDESCRIPTION32-Bit Oversampling ADC with Configurable Digital FilterThe LT C 2508-32 is a low noise, low power, high perfor-mance 32-Bit ADC with an integrated Configurable digital filter . Operating from a single supply, the LTC2508-32 features a fully differential input range up to VREF, with VREF ranging from to The LTC2508-32 supports a wide common mode range from 0V to VREF simplifying analog signal conditioning requirements. The LTC2508-32 simultaneously provides two output codes: (1) a 32-Bit digitally filtered high precision low noise code, and (2) a 22-bit no latency composite code. The Configurable digital filter reduces measurement noise by lowpass filtering and down-sampling the stream of data from the SAR ADC core, giving the 32-Bit filtered output code.

2 The 22-bit composite code consists of a 14-bit code representing the differential voltage and an 8-bit code representing the common mode voltage. The 22-bit composite code is available each conversion cycle, with no cycle of digital filter can be easily configured for 4 different down-sampling factors by pin strapping. The configura-tions provide a dynamic range of 131dB at and 145dB at 61sps. The digital lowpass filter relaxes the re-quirements for analog anti-aliasing. Multiple LTC2508-32 devices can be easily synchronized using the SYNC n INL (Typ) n145dB Dynamic Range (Typ) at 61sps n131dB Dynamic Range (Typ) at 4ksps nGuaranteed 32-Bits No Missing Codes nConfigurable Digital filter with Synchronization nRelaxed Anti-Aliasing filter Requirements nDual Output 32-Bit SAR ADC n32-Bit Digitally Filtered Low Noise Output n14-Bit Differential + 8-Bit Common Mode 1 Msps No Latency Output nWide Input Common Mode Range nGuaranteed Operation to 85 C to 5V SPI-Compatible Serial I/O nLow Power.

3 24mW at 1 Msps n24-Lead 7mm 4mm DFN Package nSeismology nEnergy Exploration nAutomated Test Equipment (ATE) nHigh Accuracy InstrumentationL, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by Patents, including 7705765, 7961132, 8319673, 8576104, 8810443, 9054727, 9231611, 9331709 and patents +IN DIFFERENTIALDIFFERENTIAL INPUTS IN+/IN WITHWIDE INPUT COMMON MODE RANGEARBITRARYUNIPOLARBIPOLARREFGNDLTC25 08-32 RDLADRLRDLBSDOASCKASCKBSDOBBUSYMCLKVDDVR EF0V0 VVREFVREF0V0 VVREFOVDD10 TO TO TA0147 F(X7R, 1210 SIZE)IN+, IN 32-BITSAR ADCCORE32-BIT14-BITPIN SELECTABLE LOW-PASS WIDEBAND DIGITAL FILTERI ntegral Nonlinearity vs Input VoltageINPUT VOLTAGE (V)250832 TA01a 5 ERROR (ppm)LTC2508-322250832fcFor more information CONFIGURATIONABSOLUTE MAXIMUM RATINGSS upply Voltage (VDD).

4 Voltage (OVDD) ..6 VReference Input (REF) ..6 VAnalog Input Voltage (Note 3) IN+, IN ..(GND ) to (REF + )Digital Input Voltage(Note 3) ..(GND ) to (OVDD + )Digital Output Voltage(Note 3) ..(GND ) to (OVDD + )Power Dissipation ..500mWOperating Temperature Range LTC2508C-32 ..0 C to 70 C LTC2508I-32 .. 40 C to 85 CStorage Temperature Range .. 65 C to 150 C(Notes 1, 2)TOP VIEW25 GNDDKD PACKAGE24-LEAD (7mm 4mm) PLASTIC DFNRDLA 1 RDLB 2 VDD 3 GND 4IN+ 5IN 6 GND 7 REF 8 REF 9 REF 10 SEL0 11 SEL1 1224 GND 23 GND22 OVDD21 BUSY20 SDOB19 SCKB18 SCKA17 SDOA16 GND15 DRL14 SYNC13 MCLK TJMAX = 125 C, JA = 40 C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONELECTRICAL CHARACTERISTICSSYMBOLPARAMETERCONDITIONS MINTYPMAXUNITSVIN+Absolute Input Range (IN+)(Note 5)l0 VREFVVIN Absolute Input Range (IN )(Note 5)

5 L0 VREFVVIN+ VIN Input Differential Voltage RangeVIN = VIN+ VIN l VREFVREFVVCMC ommon-Mode Input Range l0 VREFVIINA nalog Input Leakage Current10nACINA nalog Input CapacitanceSample Mode Hold Mode45 5pF pFCMRRI nput Common Mode Rejection RatioFiltered Output VIN+ = VIN = , 200Hz Sine128dB The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 C. (Note 4)LEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGELTC2508 CDKD-32#PBFLTC2508 CDKD-32#TRPBF25083224-Lead (7mm 4mm) Plastic DFN0 C to 70 CLTC2508 IDKD-32#PBFLTC2508 IDKD-32#TRPBF25083224-Lead (7mm 4mm) Plastic DFN 40 C to 85 CConsult LTC Marketing for parts specified with wider operating temperature ranges.

6 *The temperature grade is identified by a label on the shipping more information on lead free part marking, go to: For more information on tape and reel specifications, go to: Some packages are available in 500 unit reels through designated sales channels with #TRMPBF #orderinfoLTC2508-323250832fcFor more information ACCURACY FOR FILTERED OUTPUT (SDOA)CONVERTER CHARACTERISTICS FOR FILTERED OUTPUT (SDOA)SYMBOLPARAMETERCONDITIONSMINTYPMAX UNITSDRD ynamic RangeVREF = 5V, DF = 256 IN+ = IN = VCM, VREF = 5V, DF = 1024 IN+ = IN = VCM, VREF = 5V, DF = 4096 IN+ = IN = VCM, VREF = 5V, DF = 16384l125131 136 141 145dB dB dB dBTHDT otal Harmonic DistortionfIN = 200Hz, VREF = , DF = 256 fIN = 200Hz, VREF = 5V, DF = 256 l 118 118 108dB dBSFDRS purious Free Dynamic RangefIN = 200Hz, VREF = , DF = 256 fIN = 200Hz, VREF = 5V, DF = 256 l 108118 118dB dB 3dB Input Bandwidth34 MHzAperture Delay500psAperture Jitter4psRMST ransient ResponseFull-Scale Step125nsSYMBOLPARAMETERCONDITIONSMINTYP MAXUNITSR esolutionl32 BitsNo Missing Codesl32 BitsDFDown-sampling Factorl25616384 Transition NoiseDF = 256 (Note 6)

7 DF = 1024 DF = 4096 DF = ppm ppm ppmINLI ntegral Linearity Error(Note 7)l Error(Note 9)l 13013ppmZero-Scale Error Drift 14ppb/ CFSEFull-Scale Error(Note 9)l 100 10100ppmFull-Scale Error Drift C The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 C and AIN = 20dBFS. (Notes 4, 10) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 C.

8 (Note 4)LTC2508-324250832fcFor more information CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)REFERENCE INPUTDIGITAL INPUTS AND DIGITAL OUTPUTSSYMBOLPARAMETERCONDITIONSMINTYPMA XUNITSR esolution: Differential Common Mode l l 14 8 Bits BitsNo Missing Codes: Differential Common Mode l l 14 8 Bits BitsTransition Noise Differential Common Mode(Note 6) 1 1 LSBRMS LSBRMSINLI ntegral Linearity Error Differential Common Mode(Note 7) LSB LSBDNLD ifferential Linearity Error Differential Common Mode LSB LSBZSEZero Scale Error Differential Common Mode 1 1 LSB LSBFSEZero Scale Error Differential Common Mode 1 1 LSB LSBSYMBOLPARAMETERCONDITIONSMINTYPMAXUNI TSVREF Reference Voltage(Note 5) Input Current(Note 11) Level Input OVDDVVILLow Level Input OVDDVIIND igital Input CurrentVIN = 0V to OVDDl 1010 ACIND igital Input Capacitance5pFVOHHigh Level Output VoltageIO = 500 AlOVDD Level Output VoltageIO = 500 Output Leakage CurrentVOUT = 0V to OVDDl 1010 AISOURCEO utput Source CurrentVOUT = 0V 10mAISINKO utput Sink CurrentVOUT = OVDD10mA The

9 L denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 C. (Note 4) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 C. (Notes 4, 9) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 C.

10 (Note 4)LTC2508-325250832fcFor more information REQUIREMENTS ADC TIMING CHARACTERISTICSSYMBOLPARAMETERCONDITIONS MINTYPMAXUNITSVDDS upply IOVDD IPDS upply Current Supply Current Power Down Mode1 Msps Sample Rate 1 Msps Sample Rate (CL = 20pF) Conversion Done (IVDD + IOVDD + IREF)l 1 613 350mA mA APDP ower Dissipation Power Down Mode1 Msps Sample Rate (IVDD) Conversion Done (IVDD + IOVDD + IREF)24 875mW WSYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS fSMPLM aximum Sampling Frequencyl1 MspsfDRAO utput Data Rate at Data Rate at SDOBl1 MspstCONVC onversion Timel578652nstACQA cquisition TimetACQ = tCYC tCONV tBUSYLH (Note 8)l335nstCYCTime Between Conversionsl1000nstMCLKHMCLK High Timel20nstMCLKLM inimum Low Time for MCLK(Note 12)l20nstBUSYLHMCLK to BUSY Delay CL = 20pFl13nstDRLLHMCLK to DRL Delay CL = 20pFl18nstQUIETSCKA, SCKB Quiet Time from MCLK (Note 8)l10nstSCKASCKA Period(Notes 12, 13)l10nstSCKAHSCKA High Timel4nstSCKALSCKA Low Timel4nstDSDOASDOA Data Valid Delay from SCKA CL = 20pF, OVDD = CL = 20pF, OVDD = CL = 20pF, OVDD = l ns nstHSDOASDOA Data Remains Valid Delay from SCKA CL = 20pF (Note 8)l1nstDSDOADRLLSDOA Data Valid Delay from DRL CL = 20pF (Note 8)l5nstENAABus Enable Time After RDLA (Note 12)l16nstDISABus Relinquish Time After RDLA (Note 12)l13nstSCKBSCKB Period(Notes 12, 13)