AD9050 10-Bit, 40 MSPS/60 MSPS A/D Converter

1 FUNCTIONAL BLOCK DIAGRAMENCODEAD9050T/HADCSUMAMPDACADC+5 VDECODELOGICTIMINGAINAINB+5 VGNDREFERENCE CKTS10 REV. BInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Power: 315 mW @ 40 MSPS, 345 mW @ 60 MSPSOn-Chip T/H, ReferenceSingle +5 V Power Supply OperationSelectable 5 V or 3 V Logic I/OSNR: 53 dB Minimum at 10 MHz w/40 MSPSAPPLICATIONSM edical ImagingInstrumentationDigital CommunicationsProfessional VideoPRODUCT DESCRIPTIONThe AD9050 is a complete 10-bit monolithic sampling analog-to-digital Converter (ADC) with an onboard track-and-hold andreference. The unit is designed for low cost, high performanceapplications and requires only +5 V and an encode clock toachieve 40 MSPS or 60 MSPS sample rates with 10-bit encode clock is TTL compatible and the digital outputsare CMOS; both can operate with 5 V/3 V logic, selected by theuser.

2 The two-step architecture used in the AD9050 is opti-mized to provide the best dynamic performance available whilemaintaining low power V reference is included onboard, or the user can providean external reference voltage for gain control or matching ofmultiple devices. Fabricated on an advanced BiCMOS pro-cess, the AD9050 is packaged in space saving surface mountpackages (SOIC, SSOP) and is specified over the industrial( 40 C to +85 C) temperature range. The 60 MSPS version( AD9050 BRS-60) is only available in the SSOP package.+5V10 FENCODE(2)74AC57434105691, 7, 12,21, 23132, 8, 11,20, 22AD9050 AIN(+ )+5 VFigure 1. Typical ConnectionsOne Technology Way, Box 9106, Norwood, MA 02062-9106, : 617/329-4700 World Wide Web Site: : 617/326-8703 Analog Devices, Inc., 199710-Bit, 40 MSPS/60 MSPS A/D ConverterAD9050 SPECIFICATIONSELECTRICAL CHARACTERISTICSTest AD9050BR/BRS AD9050 BRS-60 ParameterTempLevelMinTypMaxMinTypMaxUnit sRESOLUTION1010 BitsDC ACCURACYD ifferential Nonlinearity+25 Nonlinearity+25 Missing CodesFullIVGUARANTEEDGUARANTEEDGain Error+25 CI FSGain Tempco1 FullV 100 100ppm/ CANALOG INPUTI nput Voltage Range+25 p-pInput Offset Voltage+25 CI 10+7+25 10+7+25mVFullIV 32+51 32+51mVInput Resistance+25 Input Capacitance+25 CV55pFAnalog Bandwidth+25 CV100100 MHzBANDGAP REFERENCEO utput Voltage+25 Coefficient1 FullV 50 50ppm/ CSWITCHING PERFORMANCEM aximum Conversion Rate+25 CI4060 MSPSM inimum Conversion Rate+25 Delay (tA)+25 Uncertainty (Jitter)+25 CV55ps, rmsOutput Propagation Delay (tPD)

3 2 FullIV515515nsDYNAMIC PERFORMANCET ransient Response+25 CV1010nsOvervoltage Recovery Time+25 CV1010nsENOBSfIN = MHz+25 = MHz+25 Ratio (SINAD)3fIN = MHz+25 = MHz+25 CI53555153dBSignal-to-Noise Ratio(Without Harmonics)fIN = MHz+25 CV5656dBfIN = MHz+25 Harmonic DistortionfIN = MHz+25 CV 69 69dBcfIN = MHz+25 CI 67 60 64 Harmonic DistortionfIN = MHz+25 CV 75 75dBcfIN = MHz+25 CI 70 58 62 IntermodulationDistortion (IMD)4+25 CV6565dBcDifferential Phase+25 Gain+25 B 2 (VD, VDD = +5 V; internal reference; ENCODE = 40 MSPS for BR/BRS, 60 MSPS for BRS-60unless otherwise noted)Test AD9050BR/BRS AD9050 BRS-60 ParameterTempLevelMinTypMaxMinTypMaxUnit sENCODE INPUTL ogic 1 0 1 CurrentFullIV11 ALogic 0 CurrentFullIV11 AInput Capacitance+25 CV1010pFEncode Pulse Width High (tEH)+25 Pulse Width Low (tEL)+25 OUTPUTSL ogic 1 0 1 Voltage ( VDD) 0 Voltage ( VDD) CodingOffsetBinaryCodeOffsetBinaryCodePO WER SUPPLYVD, VDD Supply Dissipation5 FullIV315400345486mWPower Supply Rejection Ratio(PSRR)6+25 CI 10 10mV/VNOTES1 Gain Tempco is for Converter only.

4 Temperature Coefficient is for bandgap reference propagation delay (tPD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF signal to rms noise with analog input signal dB below full scale at specified frequency for BR/BRS, dB below full scale for measured relative to either tone with analog input frequencies of MHz and MHz at 7 dB below full dissipation is measured at full update rate with AIN of MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at as the ratio of the change in offset voltage for 5% change in + subject to change without OF TEST LEVELSTest LevelI 100% Production Parameter is guaranteed by design and characteriza-tion Parameter is a typical value MAXIMUM RATINGS*VD, VDD .. +7 VANALOG IN .. V to VD + VDigital Inputs .. V to VDVREF Input.

5 V to VDDigital Output Current .. 20 mAOperating TemperatureAD9050BR/BRS/BRS-60 .. 40 C to +85 CStorage Temperature .. 65 C to +150 C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingsfor extended periods may effect device GUIDEM odelTemperature RangePackage Option*AD9050BR 40 C to +85 CR-28AD9050 BRS 40 C to +85 CRS-28AD9050 BRS-60 40 C to +85 CRS-28*R = Small Outline (SO); RS = Shrink Small Outline (SSOP).REV. B 3 AD9050 4 REV. BTable I. AD9050 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND)ORDigital OutputAnalog InputVoltage Level(Out of Range)MSB .. Full Scale + 1 Full Scale 1 LSB10000000000 PIN FUNCTION DESCRIPTIONSPin NoNameFunction1, 7, 12, 21, , 8, 11 VDAnalog +5 V 5% power bandgap voltage reference (nominally + V).

6 4 VREFINI nput to reference amplifier. Voltage reference for ADC is connected compensation pin, F bypass connected here to VD (+5 V).6 REFBPE xternal connection for ( F) reference bypass analog input pin (Analog input bar).10 AINA nalog input clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)on rising edge of encode of range signal. Logic 0 when analog input is in nominal range. Logic 1 whenanalog input is out of nominal (MSB)Most significant bit of ADC 19D8 D5 Digital output bits of , 22 VDDD igital output power supply (only used by digital outputs).24 27D4 D1 Digital output bits of (LSB)Least significant bit of ADC CONFIGURATION141312111098123476517161520 19182827262524232221 TOP VIEW(Not to Scale) AD9050 GNDD3D2D1D0 (LSB)VDVREFOUTVREFINVDDGNDD4 COMPREFBPGNDVDAINBAIND5 VDDGNDVDGNDENCODEORD6D9 (MSB)D8D7 WARNING!ESD SENSITIVE DEVICECAUTIONESD (electrostatic discharge) sensitive device.

7 Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without the AD9050 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of 5 REV. BNN + 1N + 2N + 3N + 4N + 5 AINENCODEDIGITALOUTPUTStAtEHtELtPDN 5N 4N 3N 2N 1 NMINTYPMAXtAAPERTURE WIDTH HIGH10ns*166nstELPULSE WIDTH LOW10ns*166nstPDOUTPUT PROP *FOR BR/BRS, SEE SPECIFICATION TABLEF igure 2. Timing Diagram8k16k8k16kAINB (Pin 9)AIN (Pin 10)INPUTBUFFERVDVDVREFIN(Pin 4)AVVREFBF(Pin 6)VDD (Pins 20, 22)+3V to +5VD0 D9, ORVDENCODE(Pin 13)VDVREFOUT(Pin 3)Figure 3. Equivalent CircuitsOutput StageEncode InputAnalog InputVREF OutputReference CircuitAD9050 Typical Performance CurvesREV.

8 B 6 TEMPERATURE C6055 40 20 SIGNAL-TO-NOISE RATIO dB(SINAD)020406080595654535857 ENCODE = 40 MSPSAIN = MHz525150 Figure 7. SNR vs. TemperatureFREQUENCY 10dB 50 60 70 30 40 20 100 110 120 80 90 ENCODE = 40 MSPSf1 IN = MHz @ 7 dBFSf2 IN = MHz @ 7 dBFS2f1 f2 = dBc2f2 f1 = dBcFigure 8. Two-Tone PHASE GAIN %123456123456 Figure 9. Differential Gain/Differential PhaseCLOCK RATE MSPS350290260010 DISSIPATION mW2030405060340300280270330310250320 5V 3 VFigure 4. Power Dissipation vs. Clock Rate1101008074686256504438dBANALOG INPUT FREQUENCY MHzHD 40 SNR 40HD 60 SNR 60 Figure 5. SNR/Distortion vs. FrequencyCLOCK RATE MSPS58500 SNR dB1020304060564846545250 SNRF igure 6. SNR vs. Clock RateAD9050 7 REV. BFREQUENCY 10dB 50 60 70 30 40 20 100 110 120 80 90 ENCODE = 40 MSPSANALOG IN = MHzSNR = dBSNR (W/O HAR) = dB2ND HARMONIC = dB3RD HARMONIC = dBFigure 10.

9 FFT Plot 40 MSPS, MHzFREQUENCY MHz020510150 10dB 50 60 70 30 40 20 100 80 90 ENCODE = 60 MSPSANALOG IN = MHzSNR = dBSNR (W/O HAR) = dB2ND HARMONIC = dB3RD HARMONIC = dB2530 Figure 11. FFT Plot 60 MSPS, MHzFREQUENCY 10dB 50 60 70 30 40 20 100 110 120 80 90 ENCODE = 40 MSPSANALOG IN = MHzSNR = dBSNR (W/O HAR) = dB2ND HARMONIC = dB3RD HARMONIC = dBFigure 12. FFT Plot 40 MSPS, MHzDUTY CYCLE %60422545405055365448 AIN = MHz306065 SIGNAL-TO-NOISE dB(SINAD)SINAD_60 SINAD_40 Figure 13. SNR vs. Clock Pulse GAIN dBANALOG INPUT FREQUENCY 14. ADC Gain vs. AIN FrequencyTEMPERATURE 40 20tPD [1] - 5V DATA RISING EDGE[2] - 5V DATA FALLING EDGE[3] - 3V DATA RISING EDGE[4] - 3V DATA FALLING [3][1][4][2]Figure 15. tPD vs. Temperature 3 V/5 VAD9050 8 REV. BTHEORY OF OPERATIONR efer to the block diagram on the front AD9050 employs a subranging architecture with digitalerror correction.

10 This combination of design techniques en-sures true 10-bit accuracy at the digital outputs of the the input, the analog signal is buffered by a high speed differ-ential buffer and applied to a track-and-hold (T/H) that holdsthe analog value present when the unit is strobed with anENCODE command. The conversion process begins on therising edge of this pulse. The two stage architecture completes acoarse and then a fine conversion of the T/H output correction and decode logic correct and align data fromthe two conversions and present the result as a 10-bit paralleldigital word. Output data are strobed on the rising edge of theENCODE command. The subranging architecture results infive pipeline delays for the output data. Refer to the AD9050 Timing THE AD90503 V SystemThe digital input and outputs of the AD9050 can be easilyconfigured to directly interface to 3 V logic systems.