DAC312 12-Bit High Speed Multiplying D/A Converter

1 REV. CInformation furnished by analog devices is believed to be accurate andreliable. However, no responsibility is assumed by analog devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of analog High Speed MultiplyingD/A ConverterDAC312 analog devices , Inc., 1996 One Technology Way, Box 9106, Norwood, MA 02062-9106, : 617/329-4700 Fax: 617/326-8703 FEATURESD ifferential Nonlinearity: 61/2 LSBN onlinearity: Settling Time: 250 nsHigh Compliance: 5 V to +10 VDifferential Outputs: 0 to 4 mAGuaranteed Monotonicity: 12 BitsLow Full-Scale Tempco: 10 ppm/8 CCircuit Interface to TTL, CMOS, ECL, PMOS/NMOSLow Power Consumption.

2 225 mWIndustry Standard AM6012 PinoutAvailable In Die FormPIN CONNECTIONS20-Pin Hermetic DIP (R-Suffix),20-Pin Plastic DIP (P-Suffix),20-Pin SOL (S-Suffix)GENERAL DESCRIPTIONThe DAC312 series of 12-Bit Multiplying digital-to- analog con-verters provide high Speed with guaranteed performance differential nonlinearity over the full commercial oper-ating temperature DAC312 combines a 9-bit master D/A Converter with a3-bit (MSBs) segment generator to form an accurate 12-Bit D/Aconverter at low cost. This technique guarantees a very uniformstep size (up to 1/2 LSB from the ideal), monotonicity to12-bits and integral nonlinearity to at its differential cur-rent outputs.

3 In order to provide the same performance with a12-bit R-2R ladder design, an integral nonlinearity over tem-perature of 1/2 LSB ( ) would be 250 ns settling time with low glitch energy and low powerconsumption are achieved by careful attention to the circuit de-sign and stringent process controls. Direct interface with allpopular logic families is achieved through the logic BLOCK DIAGRAMHigh compliance and low drift characteristics (as low as10 ppm/ C) are also features of the DAC312 along with an ex-cellent power supply rejection ratio of.

4 001% FS/% V. Oper-ating over a power supply range of +5/ 11 V to 18 V thedevice consumes 225 mW at the lower supply voltages with anabsolute maximum dissipation of 375 mW at the higher their guaranteed specifications, single chip reliability andlow cost, the DAC312 device makes excellent building blocksfor A/D converters, data acquisition systems, video display driv-ers, programmable test equipment and other applications wherelow power consumption and complete input/output versatilityare InputSlew Ratedl/dt88mA/ sPropagation DelaytPLH, tPHLAny Bit2525nsSettling TimetSTo 1/2 LSB, AllBits Switched ON250250nsor 10 10ppm/ CREV.

5 C 2 DAC312 SPECIFICATIONSELECTRICAL CHARACTERISTICS(@ VS = 615 V, IREF = mA, 08C TA +708C for DAC312E and 408C TA +858 Cfor DAC312F, DAC312H, unless otherwise noted. Output characteristics referto both IOUT and IOUT.) DAC312E DAC312F DAC312 HParameterSymbolConditionsMinTypMaxMinTy pMaxMinTypMaxUnitsResolution121212 BitsMonotonicity121212 BitsDifferential NonlinearityDNLD eviation from Ideal %FSStep Size2 1 1 LSBN onlinearityINLD eviation from Ideal Line1 Full-Scale CurrentIFSVREF = 10 VR14 = R15 = 10 k TempcoTCIFS 5 20 10 40 80ppm/ C COutput Voltage ComplianceVOCDNL Specification Guaran-teed over Compliance Range 5+10 5+10 5+10 VFull-Scale SymmetryIFSS|IFS| |IFS| 1 2

6 2 AZero-Scale ASettling TimetSTo 1/2 LSB, All BitsSwitched ON or OFF1250500250500250500nsPropagation Delay All BitstPLHAll Bits Switched 50% Point255025502550nstPHLL ogic Swing to 50% Point255025502550nsOutput1 Output ResistanceRO>10>10>10M Output CapacitanceCOUT202020pFLogic InputLevels 0 VILVLC = 1 VIHVLC = GND222 VLogic Input CurrentIINVIN = 5 to +18 V404040 ALogic Input SwingVIS 5+18 5+18 5+18 VReference Bias CurrentI150 20 20 2 AReference InputSlew Ratedl/dtR14(eq) = 800 , CC = 0 pF14 84848mA/ sPower Supply SensitivityPSSIFS+V+ = + V to + V,V = 15 V VPSSIFS V = V to V,V+ = +15 V VPower Supply RangeV+VOUT = 0 VOUT = 0 V 18 18 18 Supply CurrentI+V+ = +5 V, V = 15 V+ = +15 V, V = 15 V 18 18 13 9 18mAI+V+ = +5 V, V = 15 V+ = +15 V, V = 15 V 18 18 18mAPower DissipationPdV+ = +5 V, V = 15 V225305225305225305mWV+ = +15 V, V = 15 V267375267375267375mWTYPICAL ELECTRICAL CHARACTERISTICS@ 258C.

7 VS = 615 V, and IREF = mA, unless otherwise noted. Outputcharacteristics refer to both IOUT and CHARACTERISTICS DAC312E DAC312F DAC312 HParameterSymbolConditionsMinTypMaxMin TypMaxMinTypMaxUnitsLogic InputLevels 0 VILVLC = InputLevels 1 VIHVLC = GND222 VLogic InputCurrentIINVIN = 5 V to +18 V404040 ALogic InputSwingVIS 5+18 5+18 5+18 VReference BiasCurrentI150 20 20 2 AReference Inputdl/dtR14(eq) = 800 484848mA/ sSlew RateCC = 0 pF (Note 1)V+ = + V to + V, %FS/% VPower SupplyPSSIFS+V = 15 VSensitivityPSSIFS V = V to V, %FS/% VV+ = +15 VPower SupplyV+ VOUT = 0 V 18 18 18 + SupplyI V+ = +5 V, V = 15 V 18 18 18 CurrentI+V+ = +15 V, V = 15 18 18 18 PowerV+ = +5 V, V = 15 V225305225305225305 DissipationPdV+ = +15 V, V = 15 V267375267375267375mWNOTES1 Guaranteed by = +25 C for DAC312H grade subject to change without notice.

8 @ VS = 615 V, IREF = mA, 08C TA 708C for DAC312E and 408C TA +858C forDAC312F, DAC312H, unless otherwise noted. Output characteristics refer to both IOUT and IOUT. Continued 3 REV. CDAC312 DAC312 4 REV. CWAFER TEST LIMITSDAC312 NDAC312 GParameterSymbolConditionsLimitLimitUnit sResolution1212 Bits minMonotonicity1212 Bits minNonlinearity maxOutput VoltageFull-Scale Current+10+10V maxComplianceVocChange <1/2 LSB 5 5V minFull-ScaleVREF = maxCurrentR14, R15 = k minFull-Scale SymmetryIFSS 1 2 A maxZero-Scale A maxDifferentialDNLD eviation from maxNonlinearityIdeal Step Size 1/2 1 Bits (LSB)

9 MaxLogic Input Levels 0 VILVLC = maxLogic Input Levels 1 VIHVLC = GND22V minLogic Input SwingVIS+18+18V max 5 5V minReference BiasCurrentI15 2 2 A maxPower SupplyPSSIFS+V+ = + V to + V, V = 15 V V = V to V, V+ = +15 V SupplyI+VS = +15 V77 CurrentI IREF mA 18 18mA maxPowerVS = +15 VDissipationPDIREF mA375375mW maxNOTEE lectrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteedfor standard product dice.

10 Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.@ VS = 615 V, IREF = mA, TA = 258C, unless otherwise noted. Output characteristics refer to both IOUT and CHARACTERISTICSDIE SIZE inch, 13,536 sq. mils ( mm, sq. mm) 1. B1 (MSB)11. B11 2. B212. B12 (LSB) 3. B313. VLC/AGND 4. B414. VREF(+) 5. B515. VREF( ) 6. B616. COMP 7. B717. V 8. B818. IO 9. B919. IO10. B1020. V+ DAC312 5 REV. CORDERING GUIDE1 TemperaturePackagePackageModelDNLR angeDescriptionOptionDAC312ER2 1/2 LSB 0 C to +70 CCerdip-20Q-20 DAC312FR 1 LSB 40 C to +85 CCerdip-20Q-20 DAC312BR/883 1 LSB 55 C to +125 C Cerdip-20Q-20 DAC312HP 1 LSB 40 C to +85 CPlastic DIP-20 N-20 DAC312HS 1 LSB 40 C to +85 CSOL-20R-20 NOTES1 Burn-in is available on commercial and industrial temperature range parts incerdip, plastic DIP, and TO-can devices processed in total compliance to MIL-STD-883, add/883 after partnumber.