Triple 3-input AND gate

1 74HC11; 74 HCT11 Triple 3-input AND gateRev. 8 11 August 2021 Product data sheet1. General descriptionThe 74HC11; 74 HCT11 is a Triple 3-input AND gate. Inputs include clamp diodes. This enables theuse of current limiting resistors to interface inputs to voltages in excess of Features and benefits Wide supply voltage range from to V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC11: CMOS level For 74 HCT11: TTL level Complies with JEDEC standards: JESD8C ( V to V) JESD7A ( V to V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C3. Ordering informationTable 1. Ordering informationPackageType numberTemperature rangeNameDescriptionVersion74HC11D74 HCT11D-40 C to +125 CSO14plastic small outline package; 14 leads;body width mmSOT108-174HC11PW74 HCT11PW-40 C to +125 CTSSOP14plastic thin shrink small outline package; 14 leads;body width mmSOT402-1 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate4.

2 Functional diagrammna7933Y3C113B103A92C52B42A31C131 B21A182Y61Y12 Fig. symbolmna79212&&&68132154311109 Fig. logic symbolmna794 ABCYFig. diagram for one gate5. Pinning Pinning74HC1174 HCT111 AVCC1B1C2A1Y2B3C2C3B2Y3 AGND3Y001aal4071234567810912111413 Fig. configuration SOT108-1 (SO14)74HC11 74 HCT111 AVCC1B1C2A1Y2B3C2C3B2Y3 AGND3Y001aal4081234567810912111413 Fig. configuration SOT402-1 (TSSOP14) Pin descriptionTable 2. Pin descriptionSymbolPinDescription1A, 2A, 3A1, 3, 9data input1B, 2B, 3B2, 4, 10data inputGND7ground (0 V)1C, 2C, 3C13, 5, 11data input1Y, 2Y, 3Y12, 6, 8data outputVCC14supply voltage74HC_HCT11 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20212 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate6. Functional descriptionTable 3. Function selectionH = HIGH voltage level; L = LOW voltage level; X = don t careInputOutputnAnBnCnYLXXLXLXLXXLLHHHH7 .

3 Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).SymbolParameterConditionsMinMaxUnitVC Csupply +7 VIIK input clamping currentVI < V or VI > VCC + V[1]- 20mAIOK output clamping currentVO < V or VO > VCC + V[1]- 20mAIOoutput V < VO < VCC + V- 25mAICC supply current-50mAIGND ground current-50-mATstgstorage temperature-65+150 CPtottotal power dissipation[2]-500mW[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For SOT108-1 (SO14) package: Ptot derates linearly with mW/K above 100 SOT402-1 (TSSOP14) package: Ptot derates linearly with mW/K above 81 Recommended operating conditionsTable 5. Recommended operating conditionsVoltages are referenced to GND (ground = 0 V)74HC1174 HCT11 SymbolParameterConditionsMinTypMaxMinTyp MaxUnitVCCsupply voltage0-VCC0-VCCVVO output voltage0-VCC0-VCCVT ambambient temperature-40-+125-40-+125 CVCC = V--625---ns/VVCC = t/ Vinput transition rise and fall rateVCC = V--83---ns/V74HC_HCT11 All information provided in this document is subject to legal disclaimers.

4 Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20213 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).25 C-40 C to +85 C-40 C to +125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnit74HC11 VCC = = voltageVCC = = = voltageVCC = = VIH or VILIO = -20 A; VCC = = -20 A; VCC = = -20 A; VCC = = mA; VCC = voltageIO = mA; VCC = = VIH or VILIO = 20 A; VCC = = 20 A; VCC = = 20 A; VCC = = mA; VCC = voltageIO = mA; VCC = leakagecurrentVI = VCC or GND; VCC = V-- 1- 1 AICC supply currentVI = VCC or GND; IO = 0 A;VCC = voltageVCC = V to voltageVCC = V to = VIH or VIL; VCC = VIO = -20 voltageIO = = VIH or VIL; VCC = VVOLLOW-leveloutput voltageIO = 20 leakagecurrentVI = VCC or GND; VCC = V-- 1- 1 AICC supply currentVI = VCC or GND; IO = 0 A;VCC = A74HC_HCT11 All information provided in this document is subject to legal disclaimers.

5 Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20214 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate25 C-40 C to +85 C-40 C to +125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnit ICCadditionalsupply currentper input pin;VI = VCC - V; IO = 0 A;other inputs at VCC or GND;VCC = V to V-100360-450-490 Dynamic characteristicsTable 7. Dynamic characteristicsGND = 0 V; CL = 50 pF; for test circuit see Fig. C-40 C to +85 C-40 C to +125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnit74HC11nA, nB to nY; see Fig. 6[1]VCC = V-32100-125-150nsVCC = V-1220-25-30nsVCC = V; CL = 15 pF-9-----nstpdpropagationdelayVCC = V-1017-21-26nssee Fig. 6[2]VCC = V-1975-95-110nsVCC = V-715-19-22nstttransition timeVCC = V-613-16-19nsCPDpower dissipationcapacitanceper package;VI = GND to VCC[3]-18-----pF74 HCT11nA, nB to nY; see Fig. 6[1]VCC = V-1624-30-36nstpdpropagationdelayVCC = V; CL = 15 pF-11-----nstttransition timeVCC = V; see Fig.

6 6[2]-715-19-22nsCPDpower dissipationcapacitanceper package;VI = GND to VCC - V[3]-20-----pF[1]tpd is the same as tPHL and tPLH.[2]tt is the same as tTHL and tTLH.[3]CPD is used to determine the dynamic power dissipation (PD in W):PD = CPD x VCC 2 x fi x N + (CL x VCC 2 x fo) where:fi = input frequency in MHz;fo = output frequency in MHz;CL = output load capacitance in pF;VCC = supply voltage in V;N = number of inputs switching; (CL x VCC 2 x fo) = sum of information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20215 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND Waveforms and test circuit001aal409 VIVOHtPHLtTHLtTLHtPLHVOLGNDnA, nB, nC inputnY outputVMVMVYVXM easurement points are given in Table and VOH are typical voltage output levels that occur with the output to output propagation delaysTable 8. Measurement tWtWtrtrtfVMVI negative pulseGNDVI positive pulseGND10 %90 %90 %10 %VMVMVMtfVCCDUTRTVIVOCLGTest data is given in Table test circuit:RT = termination resistance should be equal to output impedance Zo of the pulse = load capacitance including jig and probe circuit for measuring switching timesTable 9.

7 Test dataInputLoadTypeVItr, ns15 pF, 50 pFtPLH, ns15 pF, 50 pFtPLH, tPHL74HC_HCT11 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20216 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate11. Package outlineUNIT A max. A 1 A 2 A 3 b p c D (1) E (1) (1) e H E L L p Q Z y w v REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 8 0 o o DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of mm ( inch) maximum per side are not included. SOT108-1 X w M A A 1 A 2 b p D H E L p Q detail X E Z e c L v M A (A ) 3 A 7 8 1 14 y 076E06 MS-012 pin 1 index 99-12-27 03-02-19 0 5 mm scale SO14: plastic small outline package; 14 leads; body width mm SOT108-1 Fig.

8 Outline SOT108-1 (SO14)74HC_HCT11 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20217 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gateUNIT A 1 A 2 A 3 b p c D (1) E (2) (1) e H E L L p Q Z y w v REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 8 0 o o 1 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of mm maximum per side are not included. 2. Plastic interlead protrusions of mm maximum per side are not included. SOT402-1 MO-153 99-12-27 03-02-18 w M b p D Z e 1 7 14 8 A A 1 A 2 L p Q detail X L (A ) 3 H E E c v M A X A y 0 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width mm SOT402-1 A max. pin 1 index Fig. outline SOT402-1 (TSSOP14)74HC_HCT11 All information provided in this document is subject to legal disclaimers.

9 Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20218 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate12. AbbreviationsTable 10. AbbreviationsAcronymDescriptionCMOSC omplementary Metal-Oxide SemiconductorDUTD evice Under TestESDE lectroStatic DischargeHBMH uman Body ModelMMMachine ModelTTLT ransistor-Transistor Logic13. Revision historyTable 11. Revision historyDocument IDRelease dateData sheet statusChange noticeSupersedes74HC_HCT11 data sheet-74HC_HCT11 : Section 2 updated. Type number 74HC11DB (SOT337-1/SSOP14) data sheet-74HC_HCT11 : The format of this data sheet has been redesigned to comply with the identity guidelines ofNexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74 HCT11DB (SOT337-1/SSOP14) removed. Section 7: Derating values for Ptot total power dissipation have been data sheet-74HC_HCT11 : Type numbers 74HC11N and 74 HCT11N (SOT27-1) data sheet-74HC_HCT11 : Legal pages data sheet-74HC_HCT11 data sheet-74HC_HCT11_CNV specification--74HC_HCT11 All information provided in this document is subject to legal disclaimers.

10 Nexperia 2021. All rights reservedProduct data sheetRev. 8 11 August 20219 / 11 Nexperia74HC11; 74 HCT11 Triple 3-input AND gate14. Legal informationData sheet statusDocument status[1][2]Productstatus [3]DefinitionObjective [short]data sheetDevelopmentThis document contains data fromthe objective specification forproduct [short]data sheetQualificationThis document contains data fromthe preliminary [short]data sheetProductionThis document contains the productspecification.[1]Please consult the most recently issued document before initiating orcompleting a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available onthe internet at The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodifications or additions.