16-Bit, 1 MSPS, 8-Channel, Data Acquisition System Data ...

1 16-Bit, 1 MSPS, 8- channel , data Acquisition System data sheet adas3022 . FEATURES and buffer; and a 16-bit charge redistribution analog -to-digital Ease of use 16-bit, 1 MSPS complete data Acquisition System converter (ADC) with successive approximation register (SAR). High impedance, 8- channel input: >500 M architecture. The adas3022 can resolve eight single-ended Differential input voltage range: V maximum inputs or four fully differential inputs up to V when High input common-mode rejection: >100 dB using 15 V supplies. In addition, the device can accept the User-programmable input ranges commonly used bipolar differential, bipolar single-ended, channel sequencer with individual channel gains pseudo bipolar, or pseudo unipolar input signals, as shown On-chip V reference and buffer in Table 1, thus enabling the use of almost any direct sensor Auxiliary input direct interface to PulSAR ADC inputs interface.

2 No latency or pipeline delay (SAR architecture). The adas3022 simplifies design challenges by eliminating Serial 4-wire, V to 5 V SPI-/SPORT-compatible interface signal buffering, level shifting, amplification/attenuation, LFCSP package (6 mm 6 mm). common-mode rejection, settling time, and any other analog LQFP package (7 mm 7 mm). signal conditioning challenge while allowing a smaller form 40 C to +85 C industrial temperature range factor, faster time to market, and lower cost. APPLICATIONS. Multichannel data Acquisition and System monitoring Table 1. Typical Input Range Selection Process control Signal Input Range, VIN. Power line monitoring Differential Automated test equipment 1 V V. Instrumentation V V. 5 V V. GENERAL DESCRIPTION 10 V V. The adas3022 is a complete 16-bit, 1 MSPS, successive approxi- Single Ended 1.

3 Mation based analog -to-digital data Acquisition System , which is 0 V to 1 V V. manufactured on analog devices , Inc., proprietary iCMOS high 0 V to V V. voltage industrial process technology. The device integrates an 0 V to 5 V V. 8- channel , low leakage multiplexer; a high impedance program- 0 V to 10 V V. mable gain instrumentation amplifier (PGIA) stage with high 1. See Figure 60 and Figure 61 in the analog Inputs section for more common-mode rejection; a precision, low drift V reference information. FUNCTIONAL BLOCK DIAGRAM. VDDH AVDD DVDD VIO RESET PD. DIFF DIFF TO. PAIR COM adas3022 CNV. IN0/IN1 LOGIC/ BUSY. IN0 INTERFACE. IN1. IN2/IN3 IN2 CS. IN3 SCK. MUX PGIA PulSAR. IN4/IN5 IN4 ADC. DIN. IN5. IN6 SDO. IN6/IN7. IN7. TEMP. COM SENSOR BUF REFIN. AUX+. REF. AUX.

4 10516-001. VSSH AGND DGND REFx Figure 1. Rev. D Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog devices . Tel: 2012 2018 analog devices , Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support adas3022 data sheet TABLE OF CONTENTS. Features .. 1 Typical Application Connection Diagram .. 26.

5 Applications .. 1 analog 27. General Description .. 1 Voltage Reference Output/Input .. 30. Functional Block Diagram .. 1 Power 31. Revision History .. 2 Conversion Modes .. 32. 3 Digital Interface .. 33. Timing Specifications .. 7 Conversion Control .. 33. Absolute Maximum Ratings .. 9 Reset and Power-Down (PD) Inputs .. 33. ESD Caution .. 9 Serial data Interface .. 34. Pin Configuration and Function Descriptions .. 10 General Considerations .. 35. Typical Performance Characteristics .. 12 General 36. Terminology .. 22 Configuration Register .. 38. Theory of Operation .. 24 On Demand Conversion Mode .. 39. 24 channel Sequencer Details .. 39. 24 Outline Dimensions .. 42. Transfer Function .. 25 Ordering Guide .. 42. REVISION HISTORY. 8/2018 Rev. C to Rev. D 4/2013 Rev.

6 A to Rev. B. Added LQFP Throughout Changes to Table Changes to Table 1 .. 5 Added Input Impedance of 500 M Min, Table 2 ..3. Changes to Table 3 .. 7. Changes to Figure 5, Figure 5 Caption, and Table 5 .. 11 1/2013 Rev. 0 to Rev. A. Added Figure 6; Renumbered Sequentially and Table 6; Removed Endnote 3 and Added TA = 25 C to Gain Error Test Renumbered 13 Conditions/Comments, Table Changed adas3022 Operation Section to Operation Section .. 25 Changes to REF1 and REF2 Description .. 11. Changes to Operation Section .. 25 Added Figure 25 to Figure 28; Renumbered Sequentially .. 15. Updated Outline Dimensions .. 43 Changes to Figure 15. Changes to Ordering Guide .. 43 Added Figure 30 .. 16. Changes to Figure 33, Figure 34, and Figure 35 .. 16. 2/2014 Rev. B to Rev. C Changes to Figure 36 and Figure 37.

7 17. Change to Figure 49 .. 19 Changes to Figure 19. Change to Figure 54 .. 24 Changes to Figure 24. Change to Table 7 .. 25 Changes to Figure 25. Changes to Power-Down Mode Section .. 30 Changes to Figure 57, Figure 58, Figure 59, and Figure 26. Added On Demand Conversion Mode Section and Table 12; Changes to Voltage Reference Output/Input Section, Figure 62, Renumbered 37 and Figure 28. Change to Table 13 .. 37 Changes to Core Supplies Section .. 29. Change to JEDEC Note, Figure 75 .. 40. 11/2012 Revision 0: Initial Version Rev. D | Page 2 of 42. data sheet adas3022 . SPECIFICATIONS. VDDH = 15 V 5%, VSSH = 15 V 5%, AVDD = DVDD = 5 V 5%, VIO = V to AVDD, internal reference, VREF = V, fS = 1 MSPS. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit 1.

8 RESOLUTION 16 Bits analog INPUTS IN[7:0], COM. Operating Input Voltage Range VIN VSSH + VDDH V. Differential Input Voltage Range, VIN VIN+ VIN . PGIA gain = , VIN = V p-p 6 VREF +6 VREF V. PGIA gain = , VIN = V p-p 5 VREF +5 VREF V. PGIA gain = , VIN = V p-p VREF + VREF V. PGIA gain = , VIN = V p-p VREF + VREF V. PGIA gain = , VIN = V p-p VREF + VREF V. PGIA gain = , VIN = V p-p VREF + VREF V. PGIA gain = , VIN = V p-p VREF + VREF V. Input Impedance ZIN 500 M . channel Off Leakage nA. channel On Leakage nA. Common-Mode Voltage Range 2 VIN+, VIN ; full-scale differential inputs PGIA gain = + V. PGIA gain = + V. PGIA gain = + V. PGIA gain = + V. PGIA gain = + V. analog INPUTS AUX+, AUX . Differential Input Voltage Range VREF +VREF V. THROUGHPUT. Conversion Rate One channel /one pair 0 1000 kSPS.

9 Two channels/two pairs 0 500 kSPS. Four channels/four pairs 0 250 kSPS. Eight channels 0 125 kSPS. Transient Response Full-scale step 520 ns DC ACCURACY. No Missing Codes 16 Bits Integral Linearity Error PGIA gain = , , , , 2 +2 LSB. PGIA gain = 3 +3 LSB. PGIA gain = 5 +5 LSB. Differential Linearity Error PGIA gain = , , , , + LSB. PGIA gain = + LSB. PGIA gain = + LSB. Transition Noise External reference PGIA gain = , , , , 5 LSB. PGIA gain = 7 LSB. PGIA gain = 11 LSB. Gain Error External reference, all PGIA gains, TA = 25 C 9 +9 LSB. Gain Error Temperature Drift External reference, all PGIA gains ppm/ C. Offset Error External reference, TA = 25 C. PGIA gain = , , , + + LSB. PGIA gain = + + LSB. PGIA gain = + + LSB. PGIA gain = + + LSB. Rev. D | Page 3 of 42. adas3022 data sheet Parameter Test Conditions/Comments Min Typ Max Unit 1.

10 Offset Error Temperature Drift External reference PGIA gain = , , , ppm/ C. PGIA gain = ppm/ C. PGIA gain = ppm/ C. PGIA gain = ppm/ C. Total Unadjusted Error External reference, TA = 25 C. PGIA gain = , , , , , 9 +9 LSB. PGIA gain = 15 +15 LSB. AC ACCURACY 3. Signal-to-Noise Ratio (SNR) fIN = 10 kHz PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. Signal-to-Noise-and-Distortion fIN = 10 kHz (SINAD). PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. Dynamic Range fIN = 10 kHz, 60 dB input PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. PGIA gain = dB. Total Harmonic Distortion (THD) fIN = 10 kHz, all PGIA gains 100 dB.