200 MHz Clock Generator PLL ADF4001

1 AADF4001 One Technology Way, Box 9106, Norwood, MA 02062-9106, : 781/329-4700 : Analog Devices, Inc. All rights furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices.

2 Trademarks andregistered trademarks are the property of their respective MHz Clock Generator PLLFUNCTIONAL BLOCK DIAGRAMRFINARFINB13-BITN COUNTERLOCK DETECTCURRENTSETTING 1 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4M1M3M2 SDOUTAVDDREFINCLKDATALEAVDDDVDDVPCPGNDRS ET14-BITR COUNTERR COUNTERLATCHFUNCTIONLATCH24-BITINPUT REGISTERN COUNTERLATCHSDOUT2214 ADF4001 MUXOUTMUXHIGH ZCURRENTSETTING 2 CHARGEPUMPCPCEAGNDDGNDPHASEFREQUENCYDETE CTORREFERENCE13 FEATURES200 MHz V to V Power SupplySeparate Charge Pump Supply (VP)

3 Allows ExtendedTuning Voltage in 5 V SystemsProgrammable Charge Pump Currents3-Wire Serial InterfaceHardware and Software Power-Down ModeAnalog and Digital Lock DetectHardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113 Typical Operating Current mAUltralow Phase Noise16-Lead TSSOP20-Lead LFCSPAPPLICATIONSC lock GenerationLow Frequency PLLsLow Jitter Clock SourceClock SmoothingFrequency TranslationSONET, ATM, ADM, DSLAM, SDMGENERAL DESCRIPTIONThe ADF4001 Clock Generator can be used to implement clocksources for PLLs that require very low noise, stable referencesignals.

4 It consists of a low noise digital PFD (phase frequencydetector), a precision charge pump, a programmable referencedivider, and a programmable 13-bit N counter. In addition, the14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-lockedloop) can be implemented if the synthesizer is used with an exter-nal loop filter and VCO (voltage controlled oscillator) orVCXO (voltage controlled crystal oscillator). The N minimumvalue of 1 allows flexibility in Clock 2 ADF4001 SPECIFICATIONS1(AVDD = DVDD = 3 V 10%, 5 V 10%; AVDD VP V ; AGND = DGND =CPGND = 0 V; RSET = k ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50.)

5 ParameterB VersionUnitTest Conditions/CommentsRF CHARACTERISTICS (3 V) See Figure 3 for Input CircuitRF Input Frequency5/165 MHz min/maxRF Input Sensitivity 10/0dBm min/maxRF CHARACTERISTICS (5 V)RF Input Frequency10/200 MHz min/max 5/0 dBm min/max20/200 MHz min/max 10/0 dBm min/maxREFIN CHARACTERISTICSSee Figure 2 for Input CircuitREFIN Input Frequency5/104 MHz min/maxFor f < 5 MHz, Use DC-Coupled Square Wave(0 to VDD)REFIN Input Sensitivity2 5dBm minAC-Coupled. When DC-Coupled:0 to VDD Max (CMOS Compatible)REFIN Input Capacitance10pF maxREFIN Input Current 100 A maxPHASE DETECTORP hase Detector Frequency355 MHz maxCHARGE PUMPICP Sink/SourceProgrammable: See Table VHigh Value5mA typWith RSET = k Low Value625 A typAbsolute typWith RSET = k RSET typSee Table VICP Three-State Leakage Current1nA typSink and Source Current Matching2% V VCP VP vs.

6 V VCP VP vs. Temperature2% typVCP = VP/2 LOGIC INPUTSVINH, Input High DVDDV minVINL, Input Low DVDDV maxIINH/IINL, Input Current 1 A maxCIN, Input Capacitance10pF maxLOGIC OUTPUTSVOH, Output High VoltageDVDD minIOH = 500 AVOL, Output Low maxIOL = 500 APOWER min/V min/V maxAVDD VP VIDD4 (AIDD + DIDD) mA maxTA = 25 CLow Power Sleep Mode1 A typNOISE CHARACTERISTICSADF4001 Phase Noise Floor5 161dBc/Hz typ@ 200 kHz PFD Frequency 153dBc/Hz typ@ 1 MHz PFD FrequencyPhase Noise Performance6@ VCXO Output200 MHz Output7 99dBc/Hz typ@ 1 kHz Offset and 200 kHz PFD Frequency Spurious Signals200 MHz Output7 90/ 95dBc typ/dBc typ@ 200 kHz/400 kHz and 200 kHz PFD FrequencyNOTES1 Operating temperature range (B Version) is 40 C to +85 = DVDD = 3 V.

7 For AVDD = DVDD = 5 V, use CMOS compatible by design. Sample tested to ensure = 25 C; AVDD = DVDD = 3 V; RFIN = 100 synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).6 The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 subject to change without 3 ADF4001 TIMING CHARACTERISTICSL imit atTMIN to TMAXP arameter(B Version)UnitTest Conditions/Commentst110ns minDATA to Clock Setup Timet210ns minDATA to Clock Hold Timet325ns minCLOCK High Durationt425ns minCLOCK Low Durationt510ns minCLOCK to LE Setup Timet620ns minLE PulsewidthGuaranteed by design but not production subject to change without notice.

8 (AVDD = DVDD = 3 V 10%, 5 V 10%; AVDD VP V ; AGND = DGND = CPGND= 0 V;RSET = k ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .)t1t2t3t4t6t5DB20(MSB)DB19DB2DB1(CONTRO L BIT C2)CLOCKDATALELEDB0 (LSB)(CONTROL BIT C1)Figure 1. Timing DiagramABSOLUTE MAXIMUM RATINGS1, 2(TA = 25 C, unless otherwise noted.)AVDD to GND3 .. V to +7 VAVDD to DVDD .. 0 V to + VVP to GND .. V to +7 VVP to AVDD .. V to + VDigital I/O Voltage to GND .. V to VDD + VAnalog I/O Voltage to GND.

9 V to VP + VREFIN, RFINA, RFINB to GND .. V to VDD + VRFINA to RFINB .. mVOperating Temperature RangeIndustrial (B Version) .. 40 C to +85 CStorage Temperature Range .. 65 C to +150 CMaximum Junction Temperature .. 150 CTSSOP JA Thermal Impedance .. C/WLFCSP JA Thermal Impedance (Paddle Soldered) .. 122 C/WLFCSP JA Thermal Impedance (Paddle Not Soldered) 216 C/WLead Temperature, SolderingVapor Phase (60 sec) .. 215 CInfrared (15 sec) .. 220 CNOTES1 Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device.

10 This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device device is a high performance RF integrated circuit with an ESD rating of<2 k and it is ESD sensitive. Proper precautions should be taken for handling = AGND = DGND = 0 (electrostatic discharge) sensitive device.