Transcription of 3章 実装形態 - ieice-hbkb.org
1 10 3 3 10 - 3 3 [2009 9 ] SoC SiP System in Package SiP 3 SiP Jisso 1970 DIP Dual Inline Package SOP Small Outline Package QFP Quad Flat Package BGA Ball Grid Array CSP Chip Size Package CSP WLP Wafer Level Package 1) SoC SiP 3 3 1, 2) TSV MEMS 3 SiP SoC SoC SiP 3 SiP SiP 3-1 3 3 SiP 3-2 2010 1/(6)
2 10 3 3 10 - 3 - 3 3-1 SiP [2009 9 ] SiP PCB Printed Circuit Board SoB System on Board 1 SoC SiP 3 1 SoB SoC SiP SoB PCB TAT PCB 3 1 SiP SoB SiP SoC
3 2010 2/(6) 10 3 3 45 nm 1 1 1 RF 1 SoC RF SoC IP Intellectual Property ASIC SiP RF MCP Multi Chip Package SoB SoC
4 3 PCB KGD Known Good Die SoC SoC SiP IC IC MCM IC MCM SiP 2010 3/(6) 10 3 3 10 - 3 - 3 3-2 3 3 SiP [2009 9 ] SiP MCP MCP 2 MCP SiP 3 MCP 2 MCP 3 1 2 MCP MCP PoP CoC TSV MCP 3 1 2 MCP 3 3-2-1 MCP MCP MCP 3-2-2 Package on Package (PoP)
5 Face Up 3 2010 4/(6) 10 3 3 MCP 3-2-3 Chip on Chip (CoC) Face-to-Face Face-to-Face 2 2 MCP 3) CoC 3-2-4 (TSV) MCP m TSV Through Silicon Via m m TSV CoC Face Up 3 SoC TSV 4 Via-First before FEOL Via-First after FEOL Via-Last before Stacking Via-Last after Stacking TSV TSV TSV TSV TSV 2 TSV TSV Wafer-on-Chip Wa f e r- o n - Wa f e r Pick-and-Place KGD
6 SiP 2010 5/(6) 10 3 3 Wafer-on-Chip 4) 3-2-5 3 TSV 3 SiP SoC TSV 3 SiP 3 TSV 5) m m Gbps 45 nm TSV 2 3 SiP TSV 3 2 3 2 SoC 3 SiP SiP SoC SAW/BAW MEMS 3 3 SiP SoC SoC 1) , , , , , , 2009.
7 2) N. Sillon, A. Astier, H. Boutry, L. Di Cioccio, D. Henry, P. Leduc, "Enabling Technologies for 3D Integration: From Packaging Miniaturization to Advanced Stacked ICs," IEEE International Electron Devices Meeting, , 2008. 3) M. Matsuo, N. Hayasaka, K. Okumura, E. Hosomi, C. Takubo, "Silicon Interposer Technology for High-Density Package," Electronic Components and Technology Conference, , 2000. 4) T. Fukushima,Y. Yamada, K. Kikuchi, M. Koyanagi, "New Three-Dimensional Integration Technology Using Self-Assembly Technique," IEEE International Electron Devices Meeting, , 2005. 5) K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, M. Saen, S. Komatsu, K. Osada, N. Irie, T. Hattori, A. Hasegawa, T. Kuroda, "An Inductive-Coupling Link for 3D Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM," ISSCC Digest of Technical Papers, , 2009.
8 2010 6/(6)
