Transcription of 8 章 WG7 実装 - JEITA半導体部会
1 21 8 WG7 8-1 Gordon E. Moore 1965 2 10 1975 65,000 1 10 More Moore More Moore More than Moore ITRS 2005 ITRS More Moore More than Moore More than Moore 2005 ITRS SiP (System in Package)
2 More than Moore 2007 CMOS More Moore CMOS More Moore More than Moore CMOS More than Moore System on Chip System in Package ITRS 2009 Assembly and Package (A&P) More Moore More than Moore MEMS 8-2 ITRS 4 3 6 ITRS 8-3 (SiP) SiP 6 6 SiP MCP SiP SiP (1)
3 SiP SiP 8-1 8 mm 2014 - 1 - 21 DAF (Die attach film ) 15 um 10 um DAF 15 um 8 120 um 10 um 80 um DAF 15 um 10um DAF 2014 20 um SiP 1 180 um (CoC, Face to face )
4 SiP 1 (Through silicon via, TSV) CoC PoP (Package on Package) SiP CategoryYear of Production2009201120122014201520172019pa ckage height (8 die stacked;mm) DAF thickness (um)Wire bond151510101055 Min Substrate thickness (um)All1801601401001008080 Min resin thickness over die (um)Wire bond1501008070706050 TSV--4030302018 Face to face70505050353535 Wire bond40403020202020 PoP (wire)40403020202020 PoP (FC)70505050505050 TSV--34447 Face to face2222222 Wire bond4555566 PoP2233344 Max number of die in a packageAll10121214141516 Min die thickness (um)Max number of stacked dieMobile PackagePhysicalparameters TSV ( ASET ECTC2003) Wire bonding (Cascade bonding) ( K&S) CoC (Face to Face bonding) ( )
5 PoP ( NEC ) 8- 1 SiP (1) SiP 8-2 CoC - 2 - 21 CoC SiP 200 Gbps CoC 3 I/O TSV SiP PoP PoP
6 PoP CoC TSV DDR DRAM 8-2 PoP DDR DRAM CategoryYear of Production2009201120122014201520172019 Max pin count (Logic SiP)All80090010001000100010001000 Max pin count (RF SiP)All200200200200200200200 TSV100020003000550060507,3218,858 Face to face2000250025003000300035003500 Wire bond70120150210240300370 PoP160200240240240260260 TSV--4090110160400 Face to face200300350450500550590 Wire bond21262642425252 PoP21262642425252 Max number of die-to-die bonds/SiPMax die-to-die bandwidth in SiP (Gbps)*Mobile PackageElectricalparameters 8- 2 SiP (2) (2) MCP (Multi-chip package) SSD (Solid state disk)
7 TSV SSD DDR DRAM TSV ( 8-3 ) DRAM CategoryYear of Production2009201120122014201520172019pa ckage height (8 die stacked;mm) DAF thickness (um)Wire bond151510101055 Min Substrate thickness (um)All1801601401001008080 Min resin thickness over die (um)Wire bond1501008070706050 Min die thickness (um)40403020202020 Max pin count160200240240240260260 Wire bond160200240240240260260 TSV--10001200130015001700 TSV--5991313 Wire bond10121214141516 Memory (MCP)Max number of die-to-die bondsMax number of stacked die 8- 3 SiP (3)
8 SiP SiP - 3 - 21 SiP QFP SOP ( 8-4 ) 3 SiP 3 SiP CategoryYear of Production2009201120122014201520172019 Max pin countSide by side (wire)425469492543570629693 Max number of die-to-die bonds/SiP70120150210240300370 Min die thickness (um)70505050505050 Max number of stacked die1222233 Max number of die in a package3444455 Harsh 8- 4 SiP (4) SiP SiP ( 8-5 side by side )
9 CMOS 3 LSI 3 LSI DRAM 90 C 125 C CategoryYear of Production2009201120122014201520172019 Max pin countAll3350368438604246445849045394 Passives on package Min. size (um)400X200 400 200 200X100 200 100 200 100 200 100 200 100 TSV----500060007000 Side by side (FC)5007008001000110013001500 TSV----8000900011000 Side by side (FC)1632200022002600280032003600 TSV--- -252018788 Side by side (FC)100100100100100100100 TSV--- - 235 Side by side (FC)1111111 Max number of die in a packageAll67910 High performanceMax number of die-to-die bonds/SiPMax die-to-die bandwidth in SiP (Gbps)*Min die thickness (um)
10 Max number of stacked die 8- 5 SiP SiP - 4 - 21 3 3 3 ( 8-6 ) 12 ; DDR vs.
