8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with ...

1 8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with power Scaling, kHz BW. Data Sheet AD7768/AD7768-4. FEATURES Linear phase digital filter Precision ac and dc performance Low latency sinc5 filter 8-/4-channel Simultaneous Sampling Wideband brick wall filter: dB ripple to kHz 256 kSPS maximum ADC ODR per channel analog input precharge buffers 108 dB dynamic range power supply kHz maximum input bandwidth ( 3 dB BW) AVDD1 = V, AVDD2 = V to V. 120 dB THD, typical IOVDD = V to V or IOVDD = V. 2 ppm of full-scale range (FSR) integral nonlinearity 64-lead LQFP package, no exposed pad (INL), 50 V offset error, 30 ppm gain error Temperature range: 40 C to +105 C. Optimized power dissipation vs. noise vs. input bandwidth APPLICATIONS. Selectable power , speed, and input bandwidth Fast (highest speed): kHz BW, mW per channel Data acquisition systems: USB/PXI/Ethernet Median (half speed): kHz BW, mW per channel Instrumentation and industrial control loops Low power (lowest power ): kHz BW, mW per Audio testing and measurement channel Vibration and asset condition monitoring Input BW range: dc to kHz 3-phase power quality analysis Programmable input bandwidth/ Sampling rates Sonar CRC error checking on data interface High precision medical electroencephalogram (EEG)/.

2 Daisy-chaining electromyography (EMG)/electrocardiogram (ECG). FUNCTIONAL BLOCK DIAGRAM. AVDD1A, AVDD2A, REGCAPA, AVDD1B REFx+ REFx AVDD2B REGCAPB DGND IOVDD DREGCAP. BUFFERED. VCM. PRECHARGE VCM VCM 8 REFERENCE LDO LDO. BUFFERS SYNC_IN. SYNC_OUT. START. AIN0+ P OFFSET, - DIGITAL RESET. CH 0 ADC GAIN PHASE. AIN0 P FILTER CORRECTION FORMAT1*. ENGINE. FORMAT0. AIN1+ P OFFSET, CH 1 - . ADC GAIN PHASE. AIN1 P CORRECTION ADC. OUTPUT DRDY. SINC5 DATA. AIN2+ P LOW LATENCY SERIAL DCLK. - FILTER OFFSET, CH 2 GAIN PHASE INTERFACE. ADC DOUT0. AIN2 P CORRECTION. DOUT1. AIN3+ P DOUT2. - OFFSET, CH 3 GAIN PHASE DOUT3. ADC. AIN3 P CORRECTION DOUT4*. WIDEBAND DOUT5*. AIN4+ P LOW RIPPLE DOUT6*, DIN. - OFFSET, CH 4* FILTER GAIN PHASE. ADC DOUT7*. AIN4 P CORRECTION. AIN5+ P. - OFFSET, CH 5* GAIN PHASE. AIN5 ADC ST0/CS. P CORRECTION SPI. CONTROL ST1*/SCLK. AIN6+ P INTERFACE DEC0/SDO. - OFFSET, CH 6* GAIN PHASE DEC1/SDI.

3 ADC. AIN6 P CORRECTION. AIN7+ P OFFSET, CH 7* - GAIN PHASE PIN/SPI. ADC CORRECTION. AIN7 P. 16 analog INPUT. PRECHARGE BUFFERS (P). AD7768/AD7768-4. AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 FILTER/GPIO4. 14001-001. TO. *THESE CHANNELS/PINS EXIST ONLY ON THE AD7768. MODE0/GPIO0. Figure 1. Rev. B Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog devices . Tel: 2016 2018 analog devices , Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

4 Technical Support AD7768/AD7768-4 Data Sheet TABLE OF CONTENTS. Features .. 1 AD7768 Register Map Details (SPI Control).. 78 Applications .. 1 AD7768 Register 78 Functional Block Diagram .. 1 Channel Standby Register .. 80 Revision History .. 3 Channel Mode A Register .. 80 General Description .. 5 Channel Mode B Register .. 81 6 Channel Mode Select Register .. 81 V IOVDD Specifications .. 13 power Mode Select Register .. 82 Timing Specifications .. 17 General Device Configuration Register .. 83 V IOVDD Timing Specifications .. 18 Data Control: Soft Reset, Sync, and Single-Shot Control Absolute Maximum 22 Register .. 83 Thermal Resistance .. 22 Interface Configuration 84 ESD Caution .. 22 Digital Filter RAM Built In Self Test (BIST) 85 Pin Configurations and Function Descriptions .. 23 Status Register .. 85 Typical Performance Characteristics .. 31 Revision Identification Register.

5 85 Terminology .. 41 GPIO Control Register .. 86 Theory of Operation .. 42 GPIO Write Data Register .. 86 Clocking, Sampling Tree, and power Scaling .. 42 GPIO Read Data Register .. 87 Noise Performance and 43 analog Input Precharge Buffer Enable Register Channel 0 to Channel 3 .. 87 Applications Information .. 45 analog Input Precharge Buffer Enable Register Channel 4 to power Supplies .. 46 Channel 7 .. 87 Device Configuration .. 47 Positive Reference Precharge Buffer Enable Register .. 88 Pin Control .. 47 Negative Reference Precharge Buffer Enable Register .. 88 SPI Control .. 50 Offset Registers .. 89 SPI Control Functionality .. 51 Gain Registers .. 89 SPI Control Mode Extra Diagnostic Features .. 54 Sync Phase Offset Registers .. 90 Circuit Information .. 55 ADC Diagnostic Receive Select Register .. 90 Core Signal 55 ADC Diagnostic Control Register .. 91 analog Inputs.

6 56 Modulator Delay Control 91 VCM .. 58 Chopping Control Register .. 91 Reference Input .. 58 AD7768-4 Register Map Details (SPI Control) .. 92 Clock Selection .. 58 AD7768-4 Register Map .. 92 Digital Filtering .. 58 Channel Standby Register .. 94 Decimation Rate Control .. 62 Channel Mode A Register .. 94 Antialiasing .. 62 Channel Mode B Register .. 95 Calibration .. 64 Channel Mode Select Register .. 95 Data Interface .. 66 power Mode Select Register .. 95 Setting the Format of Data Output .. 66 General Device Configuration Register .. 96 ADC Conversion Output: Header and Data .. 67 Data Control: Soft Reset, Sync, and Single-Shot Control Functionality .. 77 Register .. 97 GPIO Functionality .. 77 Interface Configuration 97 Rev. B | Page 2 of 105. Data Sheet AD7768/AD7768-4. Digital Filter RAM Built In Self Test (BIST) Register ..98 Negative Reference Precharge Buffer Enable Register.

7 101 Status Offset Revision Identification Register ..99 Gain Registers ..102 GPIO Control Register ..99 Sync Phase Offset Registers ..102 GPIO Write Data Register .. 100 ADC Diagnostic Receive Select Register ..102 GPIO Read Data Register .. 100 ADC Diagnostic Control Register ..103 analog Input Precharge Buffer Enable Register Channel 0 Modulator Delay Control Register ..104 and Channel 1 .. 100 Chopping Control analog Input Precharge Buffer Enable Register Channel 2 Outline Dimensions ..105 and Channel 3 .. 101 Ordering Guide ..105 Positive Reference Precharge Buffer Enable Register .. 101 REVISION HISTORY. 7/2018 Rev. A to Rev. B Changes to General Description Section .. 5. Changed Eco Mode to Low power Mode .. Throughout Changes to Table 1 .. 6. Changes to General Description Section .. 5 Changes to Table 2 .. 12. Changes to Table 1 .. 6 Changes to Table 3 and t30 Parameter, Table 16.

8 Changes to Table 9 ..24 Changes to Table 5 .. 17. Changes to Table 10 ..28 Changes to t30 Parameter, Table 6 and Figure 2 .. 18. Changes to Figure 73 ..45 Changes to Figure 4 and Figure 7 .. 19. Changes to MCLK Source Selection Section ..53 Changes to Figure 8 and Figure 9 .. 20. Changes to analog Inputs Section ..56 Changes to Figure 10 and Table 9 .. 22. Added Figure 87 and Table 28; Renumbered Sequentially ..57 Added Figure 11 and Table 10; Renumbered Sequentially .. 26. Changes to Table 27 ..57 Changes to Typical Performance Characteristics Section .. 30. Added Figure 88 ..58 Changes to Theory of Operation Section and Clocking, Added Filter Settling Time Section ..59 Sampling Tree, and power Scaling Section .. 41. Moved Table 29 ..60 Changes to Table 11 .. 42. Moved Table 30 ..61 Added Example of power vs. Noise Performance Optimization Changes to Modulator Saturation Point Section.

9 64 Section and Clocking Out the ADC Conversion Results Added Figure 94 ..64 (DCLK) Section .. 42. Changes to Data Interface: Standard Conversion Operation Changes to Applications Information Section and Figure 73 .. 44. Section ..68 Changes to Table 14 and power Supplies Section .. 45. Added Figure 102 ..69 Moved V IOVDD Operation Section .. 46. Added Figure 106 ..71 Changes to Figure 75, analog Supply Internal Connectivity Changes to Daisy-Chaining Section and Synchronization Section, and Pin Control Section .. 46. Section ..73 Added Figure 76 .. 47. Changes to CRC Check on Data Interface Changes to Channel Standby Section and Accessing the ADC. Added Table 38 ..74 Register Map Section .. 49. Changes to Table 43 ..81 Added Table 22 .. 49. Change to analog Input Precharge Buffer Enable Register Changes to Channel Configuration Section .. 50. Channel 0 to Channel 3 Section and analog Input Precharge Changes to Channel Modes Section, Reset over SPI Control Buffer Enable Register Channel 4 to Channel 7 Interface Section, Sleep Mode Section, and Channel Standby Change to analog Input Precharge Buffer Enable Register Section.

10 51. Channel 0 and Channel 1 Section ..98 Changes to MCLK Source Selection Section, Interface Change to analog Input Precharge Buffer Enable Register Configuration Section, and ADC Synchronization over SPI. Channel 2 and Channel 3 ..99 Section .. 52. Added Figure 81 .. 52. 3/2016 Rev. 0 to Rev. A Changes to RAM Built In Self Test Section .. 53. Added AD7768-4 .. Universal Changes to analog Inputs Section and Figure 55. Changed Precharge analog Input Reference to analog Input Added Figure 86 .. 55. Precharge .. Throughout Added Table 27 .. 56. Rev. B | Page 3 of 105. AD7768/AD7768-4 Data Sheet Changes to VCM Section, Reference Input Section, and Digital Changes to AD7768 Register Map Details (SPI Control) Section Filtering Section .. 56 and Table 37 .. 72. Changes to Figure 87, Figure 88, and Figure 89 .. 57 Changes to Channel Standby Register Section .. 74. Changes to Antialiasing Section and Modulator Sampling Changes to Table 42 and Table 43.