a 120 MHz Logarithmic Amplifier DC-Coupled …

1 ATN OUTAMPLIFIER/LIMITERFULL-WAVEDETECTORATN LOATN COMSIG +INSIG INATN COMCOM27V30V270 VATN IN1kVRG1RG0RG2 VSBL1+VSLOG OUTLOG COMSIG +OUTSIG OUTBL2 ITC201 INTERCEPT POSITIONING BIAS193241856 GAIN BIAS REGULATORAMPLIFIER/LIMITERFULL-WAVEDETEC TORAMPLIFIER/LIMITERFULL-WAVEDETECTOR10d BAMPLIFIER/LIMITERFULL-WAVEDETECTOR10dB1 0dBAMPLIFIER/LIMITERFULL-WAVEDETECTOR171 614131kV711109812 SLOPE BIAS REGULATOR1510dB10dBaDC-Coupled Demodulating120 MHz Logarithmic AmplifierAD640 One Technology Way, Box 9106, Norwood, MA 02062-9106, Tel: 781/329-4700 World Wide Web Site: Fax: 781/326-8703 Analog Devices, Inc., 1999-2016 FEATURESC omplete, Fully Calibrated Monolithic SystemFive Stages, Each Having 10 dB Gain, 350 MHz BWDirect Coupled Fully Differential Signal PathLogarithmic Slope, Intercept and AC Response areStable Over Full Military Temperature RangeDual Polarity Current Outputs Scaled 1 mA/DecadeVoltage Slope Options (1 V/Decade, 100 mV/dB, etc.)

2 Low Power Operation (Typically 220 mW at 65 V)Low Cost Plastic Packages Also AvailableAPPLICATIONSR adar, Sonar, Ultrasonic and Audio SystemsPrecision Instrumentation from DC to 120 MHzPower Measurement with Absolute CalibrationWide Range High Accuracy Signal CompressionAlternative to Discrete and Hybrid IF StripsReplaces Several Discrete Log Amp ICsPRODUCT DESCRIPTIONThe AD640 is a complete monolithic Logarithmic Amplifier . A singleAD640 provides up to 50 dB of dynamic range for frequenciesfrom dc to 120 MHz. Two AD640s in cascade can provide up to95 dB of dynamic range at reduced bandwidth. The AD640 uses asuccessive detection scheme to provide an output current propor-tional to the logarithm of the input voltage. It is laser calibrated toclose tolerances and maintains high accuracy over the full militarytemperature range using supply voltages from V to AD640 comprises five cascaded DC-Coupled Amplifier /limiterstages, each having a small signal voltage gain of 10 dB and a 3 dBbandwidth of 350 MHz.

3 Each stage has an associated full-wavedetector, whose output current depends on the absolute value of itsinput voltage. The five outputs are summed to provide the videooutput (when low-pass filtered) scaled at 1 mA per decade (50 Aper dB). On chip resistors can be used to convert this output cur-rent to a voltage with several convenient slope options. A balancedsignal output at +50 dB (referred to input) is provided to operateAD640s in Logarithmic response is absolutely calibrated to within 1 dBfor dc or square wave inputs from mV to 200 mV, withan intercept ( Logarithmic offset) at 1 mV dc. An integral X10attenuator provides an alternative input range of mV to 2 V dc. Scaling is also guaranteed for sinusoidal AD640B is specified for the industrial temperature range of 40 C to +85 C and the AD640T, available processed to MIL-STD-883B, for the military range of 55 C to +125 C. Both areavailable in 20-lead side-brazed ceramic DIPs or leadless chipcarriers (LCC).

4 The AD640J is specified for the commercialtemperature range of 0 C to +70 C, and is available in both20-lead plastic DIP (N) and PLCC (P) device is now available to Standard Military Drawing(DESC) number 5962-9095501 MRA and HIGHLIGHTS1. Absolute calibration of a wideband Logarithmic Amplifier isunique. The AD640 is a high accuracy measurement device,not simply a Logarithmic building Advanced design results in unprecedented stability over thefull military temperature The fully differential signal path greatly reduces the risk ofinstability due to inadequate power supply decoupling andshared ground connections, a serious problem with com-monly used unbalanced Differential interfaces also ensure that the appropriate groundconnection can be chosen for each signal port. They furtherincrease versatility and simplify applications. The signal inputimpedance is ~500 k in shunt with ~2 The DC-Coupled signal path eliminates the need for numerousinterstage coupling capacitors and simplifies logarithmicconversion of subsonic signals.

5 (continued on page 4)FUNCTIONAL BLOCK DIAGRAMREV. DInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog SPECIFICATIONSDC SPECIFICATIONSM odel AD640J AD640 BAD640 TParameterConditionsMinTypMaxMinTypMaxMi nTypMaxUnitsTRANSFER FUNCTION1 IOUT = IY LOG |VIN/VX| for VIN = mV to 200 mV dcSIGNAL INPUTS (Pins 1, 20)Input ResistanceDifferential500500500k Input Offset VoltageDifferential505005020050200 Vvs. V/ COver TemperatureTMIN to TMAX300 Vvs. Supply222 V/VInput Bias Current725725725 AInput Bias Offset111 ACommon-Mode Range 2+ 2+ 2+ ATTENUATOR(Pins 2, 3, 4, 5 and 19)Attenuation2 Pin 5 to Pin 19202020dBInput ResistancePins 5 to 3/4300300300 SIGNAL OUTPUT (Pins 10, 11)Small Signal Gain3505050dBPeak Differential Output4 180 180 180mVOutput ResistanceEither Pin to COM757575 Quiescent Output VoltageEither Pin to COM 90 90 90mVLOGARITHMIC OUTPUT5 (Pin 14)Voltage Compliance Range +VS 1 +VS 1 1 VSlope Current, vs.

6 CTMIN to vs. Supply+VS = V to Voltage6, V/ COver TemperatureTMIN to Supply VS = V to V222 V/VLogarithmic Offset(Alt. Definition of VX) COver TemperatureTMIN to TMAX Supply VS = V to Voltage Using Signal Output Current7 DisabledPin 8 to COM Output RESISTORS(Pins 15, 16, 17) DC LINEARITYVIN 1 mV to 100 ABSOLUTE DCACCURACYVIN = 1 mV to 100 TemperatureTMIN to Supply Range VS = V to = mV to 200 AttenuatorVIN = 10 mV to 1 TemperatureTMIN to = mV to 2 REQUIREMENTSV oltage Supply Current9+VS (Pin 12)TMIN to TMAX915915915mA VS (Pin 7)TMIN to TMAX356035603560mA 2 REV. D(VS = 65 V, TA = +258C, unless otherwise noted)AC SPECIFICATIONSM odel AD640J AD640 BAD640 TParameterConditionsMinTypMaxMinTypMaxMi nTypMaxUnitsSIGNAL INPUTS (Pins 1, 20)Input CapacitanceEither Pin to COM222pFNoise Spectral Density1 kHz to 10 MHz222nV/ HzTangential SensitivityBW = 100 MHz 72 72 72dBm3 dB BANDWIDTHEach Stage350350350 MHzAll Five StagesPins 1 & 20 to 10 & 11145145145 MHzLOGARITHMIC OUTPUTS5 Slope Current, IYf< = 1 = 30 = 60 = 90 = 120 , Dual AD640s10, 11f< = 1 MHz = 30 MHz = 60 MHz = 90 MHz = 120 MHz LINEARITY 40 dBm to 2 dBm12f = 1 35 dBm to 10 dBm12f = 1 75 dBm to 0 dBm10f = 1 70 dBm to 10 dBm10f = 1 75 dBm to +15 dBm13f = 10 OPTION AD640TD AD640BE AD640TE AD640]N20-Lead Ceramic SBDIP Package (D) 20-Terminal Ceramic LCC (E)20-Lead Plastic DIP Package (N)20-Lead Plastic Leaded Chip Carrier (P)

7 AD640JP AD640 BPNUMBER OF TRANSISTORS155155155 NOTES1 Logarithms to base 10 are used throughout. The response is independent of the sign of ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of + gain is trimmed using a 200 V square wave at 2 kHz, corrected for the onset of fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute defined as flowing into Pin 14. See FUNDAMENTALS OF Logarithmic CONVERSION for full explanation of scaling concepts. Slope is measuredby linear regression over central region of transfer Logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG10 (VX/1 V).7 The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is in circuit of Figure 24 using accurate values for RLA and RLB. Includes slope and nonlinearity errors. Input offset errors also included forVIN >3 mV dc, and over the full input range in ac independent of supply the circuit of Figure 27, using cascaded AD640s and offset nulling.

8 Input is sinusoidal, 0 dBm in 50 = 223 mV a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept for dual AD640 the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 = 223 mV the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculateoutgoing quality subject to change without CHARACTERISTICSuJC (8C/W)uJA (8C/W)25852585246120-Lead Ceramic SBDIP Package (D-20)20-Terminal Ceramic LCC (E-20-1)20-Lead Plastic DIP Package (N-20)20-Lead Plastic Leaded Chip Carrier (P-20)2875AD640 REV. D 3 (VS = 65 V, TA = +258C, unless otherwise noted)AD640 REV. D 4 CHIP DIMENSIONS ANDBONDING DIAGRAMD imensions shown in inches and (mm).ABSOLUTE MAXIMUM RATINGS*Supply Voltage.

9 VInput Voltage (Pin 1 or Pin 20 to COM) .. 3 V to +300 mVAttenuator Input Voltage (Pin 5 to Pin 3/4) .. 4 VStorage Temperature Range D, E .. 65 C to +150 CStorage Temperature Range N, P .. 65 C to +125 CAmbient Temperature Range, Rated PerformanceIndustrial, AD640B .. 40 C to +85 CMilitary, AD640T .. 55 C to +125 CCommercial, AD640J .. 0 C to +70 CLead Temperature Range (Soldering 60 sec) .. +300 C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.(continued from page 1)6. The low input offset voltage of 50 V (200 V max) ensuresgood accuracy for low level dc Thermal recovery tails, which can obscure the responsewhen a small signal immediately follows a high level input,have been minimized by special attention to design The noise spectral density of 2 nV/ Hz results in a noise floor of~23 V rms ( 80 dBm) at a bandwidth of 100 MHz.

10 The dy-namic range using cascaded AD640s can be extended to 95 dBby the inclusion of a simple filter between the two CAUTION CONNECTION DIAGRAMS 20-Lead PLCC (P) Package20-Terminal Ceramic LCC (E) Package20-Lead Ceramic SBDIP (D) Package 20-Lead Plastic DIP (N) Package9 10 11 12 133 2 1 20 19181716151445678 TOP VIEW(Not to Scale)PIN 1 IDENTIFIERAD640 ATN COMCKT COMATN COMATN LOBL2 SIG INSIG +INATN OUTRG1RG0RG2 LOG OUTSIG OUTSIG +OUT+VSLOG COMATN INBL1 VSITCTOP VIEW(Not to Scale)2019181716151413121112345678910AD6 40 SIG OUTBL2 ITCATN LOATN COMATN COM VSBL1 ATN INSIG INSIG +INATN OUTCKT COMRG1RG0RG2 LOG OUTLOG COM+VSSIG +OUT20191231814151617456789 10111213 TOP VIEW(Not to Scale)AD640 ATN COMCKT COMATN COMATN LOBL2 SIG INSIG +INATN OUTRG1RG0RG2 LOG OUTSIG OUTSIG +OUT+VSLOG COMATN INBL1 VSITCT ypical DC Performance Characteristics AD640 REV. D 5 60 40 200 20 40 60 80 100 120 140 TEMPERATURE 8 CSLOPE CURRENT mAFigure 1.