a 16-Channel, 8-Bit Multiplying DAC AD8600

1 One Technology Way, Box 9106, Norwood. MA 02062-9106, : 617/329-4700 Fax: 617/326-8703 FUNCTIONAL BLOCK DIAGRAMR/W VDD1 LDCONTROL LOGIC ADDRESSDECODE16 x 8 INPUTREGISTERSRS VDD2 VREFVCC16 x 8 DACREGISTERS168-BITDACSCS EN A3A2A1A0 DB7DB6DB5DB4DB3DB2DB1DB0O0O1O2O3O4O5O6O7 O8O9O10O11O12O13O14O15 VEEDGND1 DGND2 DACGNDAD8600 REV. 0 Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog.

2 8-BitMultiplying DACAD8600 FEATURES16 Independently Addressable Voltage OutputsFull-Scale Set by External Reference2 s Settling TimeDouble Buffered 8-Bit Parallel InputHigh Speed data Load RateData ReadbackOperates from Single +5 VOptional 6 V Supply Extends Output RangeAPPLICATIONSP hased Array Ultrasound & SonarPower Level SettingReceiver Gain SettingAutomatic Test EquipmentLCD Clock Level SettingGENERAL DESCRIPTIONThe AD8600 contains 16 independent voltage output digital-to-analog converters that share a common external reference inputvoltage. Each DAC has its own DAC register and input registerto allow double buffering.

3 An 8-Bit parallel data input, four ad-dress pins, a CS select, a LD, EN, R/W, and RS provide thedigital AD8600 is constructed in a monolithic CBCMOS processwhich optimizes use of CMOS for logic and bipolar for speedand precision. The digital-to-analog converter design uses volt-age mode operation ideally suited to single supply internal DAC voltage range is fixed at DACGND to voltage buffers provide an output voltage range that ap-proaches ground and extends to V below VCC. Changes inreference voltage values and digital inputs will settle within 1 LSB in 2 is preloaded into the input registers one at a time after theinternal address decoder selects the input register.

4 In the writemode (R/W low) data is latched into the input register duringthe positive edge of the EN pulse. Pulses as short as 40 ns canbe used to load the data . After changes have been submitted tothe input registers, the DAC registers are simultaneously up-dated by a common load EN LD strobe. The new analog out-put voltages simultaneously appear on all 16 system power up or during fault recovery the reset (RS) pinforces all DAC registers into the zero state which places zerovolts at all DAC AD8600 is offered in the PLCC-44 package. The device isdesigned and tested for operation over the extended industrialtemperature range of 40 C to +85 CS ADDRESS RS VDD2 VREFVCCDGND2 DGND1R-2 RDAC LD ENVEERSR/W CS ADDR EN 1.

5 Equivalent DAC Channel AD8600 SPECIFICATIONSSINGLE SUPPLYP arameterSymbolConditionMinTypMaxUnitsSTA TIC PERFORMANCE1 ResolutionN8 BitsRelative Accuracy2 INL 1 1/2+1 LSBD ifferential Nonlinearity2 DNLG uaranteed Monotonic 1 1/4+1 LSBFull-Scale VoltageVFSData = TempcoTCVFSData = FFH 20ppm/ CZero Scale ErrorVZSEData = 00H, RS = 0, TA= +25 C+ = 00H, RS = 0 +5 LSBR eference Input ResistanceRREFData = ANALOG OUTPUTO utput Voltage Range2 OVRSSVREF = + CurrentIOUTData = 80H 2mACapacitive LoadCLNo Oscillation50pFLOGIC INPUTSL ogic Input Low Input High Input CurrentIIL10 ALogic Input Capacitance3 CIL10pFLOGIC OUTPUTSL ogic Out High VoltageVOHIOH = Out Low VoltageVOLIOL = CHARACTERISTICS3 Slew RateSRFor VREF or FS Code Change47V/ sVoltage Output Settling Time2tS1 1 LSB of Final Value, Full-Scale data Change2 sVoltage Output Settling Time2tS2 1 LSB of Final Value, VREF = 1 V, data = FFH2 sPOWER SUPPLIESP ositive Supply CurrentICCVIH = 5 V.

6 VIL = 0 V, No Load2435mALogic Supply CurrentsIDD1&2 VIH = 5 V, VIL = 0 V, No DissipationPDISSVIH = 5 V, VIL = 0 V, No Load120175mWPower Supply SensitivityPSS VCC = 5% Power Supply Power Supply VREF = V, 1 LSB = supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (VEE) pin of at least V to V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 710 to by design not subject to production subject to change without 0 2 (@ VDD1 = VDD2 = VCC = +5 V 5%, VEE = 0 V, VREF = + V, 40 C TA +85 C, unless otherwise noted)

7 ParameterSymbolConditionMinTypMaxUnitsST ATIC PERFORMANCE1 ResolutionN8 BitsTotal Unadjusted ErrorTUEAll Other DACs Loaded with data = 55H 1 3/4+1 LSBR elative AccuracyINL 1 1/2+1 LSBD ifferential NonlinearityDNLG uaranteed Monotonic 1 1/4+1 LSBFull-Scale VoltageVFSData = FFH, VREF = + Voltage ErrorVFSEData = FFH, VREF = + V 1+1 LSBFull-Scale TempcoTCVFSData = FFH, VREF = + V 20ppm/ CZero Scale ErrorVZSEData = 00H, RS = 0, TA = +25 C 2 1+2 mVZero Scale ErrorVZSEData = 00H, All Other DACs data = 00H 1+1 LSBZero Scale ErrorVZSEData = 00H, All Other DACs data = 55H 1/2 LSBZero Scale TempcoTCVZSData = 00H, VCC = +5 V, VEE = 5 V 10 V/ CReference Input ResistanceRREFData = Reference Input Capacitance2 CREFData = ABH240pFANALOG OUTPUTO utput Voltage RangeOVR1 VREF = + Voltage Range2 OVR2 VCC = VDD2 = +7 V, VEE = V, VREF = 5 CurrentIOUTData = 80H 2mACapacitive Load2 CLNo Oscillation50pFLOGIC INPUTSL ogic Input Low Input High Input CurrentIIL10 ALogic Input Capacitance2 CIL10pFLOGIC OUTPUTSL ogic Out High VoltageVOHIOH = Out Low VoltageVOLIOL = CHARACTERISTICS2 Reference In BandwidthBW 3 dB Frequency.

8 VREF = VDC + VAC500kHzSlew RateSRFor VREF or FS Code Change47V/ sVoltage Noise DensityeNf = 1 kHz, VREF = 0 V46nV/ HzDigital FeedthroughFTDigital Inputs to DAC Outputs10nVsVoltage Output Settling Time3tS1 1 LSB of Final Value, FS data Change12 sVoltage Output Settling Time3tS2 1 LSB of Final Value, VREF = 1 V, data = FFH12 sPOWER SUPPLIESP ositive Supply CurrentICCVIH = 5 V, VIL = 0 V, VEE = 5 V, No Load2235mANegative Supply CurrentIEEVIH = 5 V, VIL = 0 V, VEE = 5 V, No Load2235mALogic Supply CurrentsIDD1&2 VIH = 5 V, VIL = 0 V, VEE = 5 V, No Dissipation4 PDISSVIH = 5 V, VIL = 0 V, VEE = 5 V, No Load225350mWPower Supply SensitivityPSS VCC & VEE = 5% Power Supply Power Supply Power Supply Range2 VEER VREF = + V, 1 LSB = by design not subject to production time test is performed using RL = 50 k and CL = 35 Dissipation is calculated using 5 V (IDD + |ISS| + IDD1 + IDD2).

9 Specifications subject to change without SUPPLY(@ VDD1 = VDD2 = VCC = +5 V 5%, VEE = 5 V 5%, VREF = + V, 40 C TA +85 C, unless otherwise noted) AD8600 REV. 0 3 REV. 0 4 AD8600 ELECTRICAL CHARACTERISTICSP arameterSymbolConditionMinTypMaxUnitsINT ERFACE TIMING1, 2 Clock (EN) FrequencyfCLKData (EN) High Pulse WidthtCH40nsClock (EN) LowPulse WidthtCL40nsData Setup TimetDS40nsData Hold TimetDH10nsAddress Setup TimetAS0nsAddress Hold TimetAH0nsValid Address to data ValidtAD160nsLoad Enable Setup TimetLS0nsLoad Enable Hold TimetLH0nsRead/Write to Clock (EN)tRWC30nsRead/Write to DataBus Hi-ZtRWZ120nsRead/Write to DataBus ActivetRWD120nsClock (EN) to Read/WritetTWH0nsClock (EN) to Chip SelecttTCH0nsChip Select to Clock (EN)

10 TCSC30nsChip Select to data ValidtCSD120nsChip Select to DataBus Hi-ZtCSZ150nsReset Pulse WidthtRS25nsNOTES1 Guaranteed by design not subject to production logic input signals have maximum rise and fall times of 2 subject to change without 3. Readback TimingFigure 2. Write Timing(@ VDD1 = VDD2 = VCC = +5 V 5%, VEE = 5 V, VREF = + V, 40 C TA +85 C,unless otherwise noted)tRWZtDHtTWHHIGH-ZtAStAHtCHtCLtTCHR /WDATAADDRENCStCSCtRWCtDSFigure 4. Write to DAC Register & Voltage Output SettlingTiming (CS= High, Prevents Input Register Changes)tLStLHtS1tRSOUTtS1 ENRSLDtRWDHIGH -ZtADtCSZtCSDR/WDATAADDRENCSAD8600 REV.