a 2-Channel, 256-Position Digital Potentiometer …

1 REV. 0 Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Technology Way, Box 9106, Norwood, MA 02062-9106, : 781 : 781/326-8703 Analog Devices, Inc., 20012- channel , 256-PositionDigital PotentiometerFUNCTIONAL BLOCK DIAGRAMRDAC1 REGISTERRRDAC2 REGISTERRPOWER-ONRESETLOGICSERIAL INPUT REGISTERAD52078 SDODGNDSDICSVSSSHDNVDDA1W1B1A2W2B2 CLKFEATURES256-Position, 2-ChannelPotentiometer Replacement10 k , 50 k , 100 k Power Shut-Down, Less than 5 V to V Single Supply V Dual Supply3-Wire SPI-Compatible Serial Data InputMidscale Preset During Power-OnAPPLICATIONSM echanical Potentiometer ReplacementStereo channel Audio Level ControlInstrumentation.

2 Gain, Offset AdjustmentProgrammable Voltage-to-Current ConversionProgrammable Filters, Delays, Time ConstantsLine Impedance MatchingAutomotive Electronics AdjustmentGENERAL DESCRIPTIONThe AD5207 provides dual channel , 256-Position , digitallycontrolled variable resistor (VR) devices that perform the sameelectronic adjustment function as a Potentiometer or variableresistor. Each channel of the AD5207 contains a fixed resistor witha wiper contact that taps the fixed resistor value at a pointdetermined by a Digital code loaded into the SPI-compatibleserial-input register. The resistance between the wiper and eitherend point of the fixed resistor varies linearly with respect to thedigital code transferred into the VR latch. The variable resistoroffers a completely programmable value of resistance, betweenthe A Terminal and the wiper or the B Terminal and the fixed A-to-B terminal resistance of 10 k , 50 k or 100 k has a 1% channel -to- channel matching tolerance with a nomi-nal temperature coefficient of 500 ppm/ C.

3 A unique switchingcircuit minimizes the high glitch inherent in traditional switchedresistor designs and avoids any make-before-break or break-before-make VR has its own VR latch, which holds its programmedresistance value. These VR latches are updated from an internalserial-to-parallel shift register, which is loaded from a standard3-wire serial-input Digital interface. Ten bits, to make up thedata word, are required and clocked into the serial input first two bits are address bits. The following eight bits arethe data bits that represent the 256 steps of the resistance reason for two address bits instead of one is to be compatiblewith similar products such as AD8402 so that drop-in replacementis possible. The address bit determines the corresponding VRlatch to be loaded with the data bits during the returned positiveedge of CS strobe. A serial data output pin at the opposite endof the serial register allows simple daisy chaining in multipleVR applications without additional external decoding internal reset block will force the wiper to the midscale posi-tion during every power-up condition.

4 The SHDN pin forces anopen circuit on the A Terminal and at the same time shorts thewiper to the B Terminal, achieving a microwatt power shutdownstate. When SHDN is returned to logic high, the previous latchsettings put the wiper in the same resistance setting prior toshutdown. The Digital interface remains active during shutdown;code changes can be made to produce new wiper positions whenthe device is resumed from AD5207 is available in mm thin TSSOP-14 package,which is suitable for PCMCIA applications. All parts are guaran-teed to operate over the extended industrial temperature rangeof 40 C to +125 0 2 AD5207 SPECIFICATIONSELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k VERSION (VDD = 5 V, VSS = 0, VA = 5 V,VB = 0, 40 C < TA < +125 C unless otherwise noted.)ParameterSymbolConditionsMinTyp1 MaxUnitDC CHARACTERISTICSRHEOSTAT MODES pecifications Apply to All VRsResistor Differential Nonlinearity2R-DNLRWB, VA = NC 1+1 LSBR esistor Nonlinearity2R-INLRWB, VA = NC + Resistor Tolerance3 R 30+30%Resistance Temperature CoefficientRAB/ TVAB = VDD, Wiper = No Connect500ppm/ CWiper ResistanceRWIW = 1 V/R, VDD = 5 V50100 Nominal Resistance Match R/ROCh 1 to 2, VAB = VDD, TA = 25 CHARACTERISTICSPOTENTIOMETER DIVIDER MODES pecifications Apply to All VRsResolutionN8 BitsIntegral Nonlinearity4 INL + Nonlinearity4 DNLVDD = 5 V, VSS = 0 V 1+1 LSBV oltage Divider Temperature VW/ TCode = 80H15ppm/ CCoefficientFull-Scale ErrorVWFSECode = FFH ErrorVWZSECode = 00H+ TERMINALSV oltage Range5VA, B, W|VDD| + |VSS| VVSSVDDVC apacitance6 AX, BXCA,Bf = 1 MHz, Measured to GND, Code = 80H45pFCapacitance6 WXCWf = 1 MHz.

5 Measured to GND, Code = 80H70pFShutdown Current7IA_SDVA = VDD, VB = 0 V, SHDN = 05 AShutdown Wiper ResistanceRW_SDVA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V200 Common-Mode LeakageICMVA = VB = VDD/21nADIGITAL INPUTS AND OUTPUTSI nput Logic HighVIHVDD = 5 V, VSS = 0 Logic LowVILVDD = 5 V, VSS = 0 Logic HighVIHVDD = 3 V, VSS = 0 Logic LowVILVDD = 3 V, VSS = 0 Logic HighVOHRL = 1 k to VDDVDD Logic LowVOLIOL = mA, VDD = 5 CurrentIILVIN = 0 V or 5 V 10 AInput Capacitance6 CIL10pFPOWER SUPPLIESP ower Single-Supply RangeVDD RANGEVSS = 0 Dual-Supply RangeVDD/SS RANGE Supply CurrentIDDVIH = VDD or VIL = GND, VSS = 0 V40 ANegative Supply CurrentISSVIH = VDD or VIL = GND VSS = V40 APower Dissipation8 PDISSVIH = 5 V or VIL = 0 V, VDD = 5 Supply Sensitivity, VDDPSS VDD = 5 V 10%, VSS = 0 V, Code = Supply Sensitivity, VSSPSS VSS = V 10%, VDD = V, Code = CHARACTERISTICS6, 9 Bandwidth 3 dBBW_10 k RAB = 10 k 600kHzBandwidth 3 dBBW_50 k RAB = 50 k 125kHzBandwidth 3 dBBW_100 k RAB = 100 k 71kHzTotal Harmonic DistortionTHDWVA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k Settling TimetSRAB = 10 k /50 k /100 k , 1 LSB Error Band2/9/18 sResistor Noise VoltageeN_WBRWB = 5 k , f = 1 kHz, RS = 09nV HzCrosstalk10 CTVA = 5 V, VB = 0 V 65dBREV.

6 0 3 AD5207 ParameterSymbolConditionsMinTyp1 MaxUnitINTERFACE TIMINGCHARACTERISTICSA pplies to All Parts6, 11 Input Clock PulsewidthtCH, tCLClock Level High or Low10nsData Setup TimetDS5nsData Hold TimetDH5nsCLK to SDO Propagation Delay12tPDRL = 1 k to 5 V, CL < 20 pF125nsCS Setup TimetCSS10nsCS High PulsewidthtCSW10nsCLK Fall to CS Fall Hold TimetCSH00nsCLK Fall to CS Rise Hold TimetCSH10nsCS Rise to Clock Rise SetuptCS110nsNOTES1 Typicals represent average readings at 25 C and VDD = 5 V, VSS = 0 position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiperpositions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = 5 V,VSS = 0 = VDD, Wiper (VW) = No and DNL are measured at VW with the RDAC configured as a Potentiometer divider similar to a voltage output D/A converter.

7 VA = VDD and VB = 0 V. DNLspecification limits of 1 LSB maximum are Guaranteed Monotonic operating Terminals A, B, W have no limitations on polarity with respect to each by design and not subject to production at the AX terminals. All AX terminals are open-circuited in shut-down is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dynamic characteristics use VDD = 5 V, VSS = 0 at a VW pin where an adjacent VW pin is making a full-scale voltage timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level V. Switching characteristics are measured using VDD = 5 delay depends on value of VDD, RL, and CL; see applications AD5207 contains 474 transistors. Die Size: 67 mil 69 mil, 4623 sq. subject to change without REGISTER LOADA1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Figure Diagram10101010 VDD0 VSDI(DATA IN)SDO(DATA OUT)CLKCSVOUTAx OR DxAx OR DxA'x OR D'xA'x OR D'x 1 LSB ERROR BAND 1 LSBtDStDHtPD_MAXtCS1tCSH1tCSWtStCLtCHtCS H0tCSSF igure Timing DiagramREV.

8 0AD5207 4 CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD5207 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of !ESD SENSITIVE DEVICEABSOLUTE MAXIMUM RATINGS1(TA = 25 C, unless otherwise noted)VDD to GND .. , +7 VVSS to GND .. 0, 3 VVDD to VSS .. 7 VVA, VB, VW to GND .. VSS, VDDIMAX2 (A, B, W) .. 20 mADigital Inputs and Output Voltage to GND .. 0 V, VDD + VOperating Temperature Range .. 40 C to +125 CMaximum Junction Temperature (TJ Max) .. 150 CStorage Temperature.

9 65 C to +150 CLead Temperature (Soldering, 10 sec) .. 300 CThermal Resistance3 JA, TSSOP-14 .. 206 C/WNOTES1 Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device current is bounded by the maximum current handling of the switches,maximum power dissipation of the package, and maximum applied voltageacross any two of the A, B, and W Terminals at a given resistance. Please refer toTPC 22 for Power Dissipation = (TJ Max TA)/ FUNCTION DESCRIPTIONSPin Mnemonic Description1 VSSN egative Power Supply, specified for opera-tion from 0 V to B of RDAC# A of RDAC# , RDAC#2, addr = 125 DGNDD igital Low Input.

10 Terminal A open-circuitand Terminal B shorted to Wiper. Shut-down controls both RDACs #1 and # Select Input, Active Low. When CSreturns high, data in the serial input registeris decoded, based on the address bit, andloaded into the corresponding RDAC Data Input. MSB is loaded Data Output. Open Drain transistorrequires pull-up Clock Input. Positive Edge Power Supply. Specified for opera-tion at V to , RDAC #1, addr = A of RDAC # B of RDAC # I. Serial-Data Word Format ADDR DATAB9B8B7B6B5B4B3B2B1B0A1A0D7D6D5D4D3D2 D1D0 MSBLSB29282720 NOTESADDR(RDAC1) = 00; ADDR(RDAC2 = 01).Data loads B9 first into SDI CONFIGURATIONTOP VIEW(Not to Scale)1413121110981234567B1 VSSAD5207A1B2W1A2 VDDW2 CLKDGNDSDOSHDNSDICSORDERING GUIDET emperaturePackagePackageQty PerBrandingModelk RangeDescriptionOptionContainerInformati on*AD5207 BRU10-REEL710 40 C to +125 CTSSOP-14RU-141,000B10AD5207 BRU50-REEL750 40 C to +125 CTSSOP-14RU-141,000B50AD5207 BRU100-REEL7100 40 C to +125 CTSSOP-14RU-141,000B100*Three lines of information appear on the device.