a APPLICATION NOTE AN-543 - Analog Devices

1 AAN-543 APPLICATION NOTEOne Technology Way Box 9106 Norwood, MA 02062-9106 781/329-4700 World Wide Web Site: following describes the implementation of a highquality all-digital FM RF generator for use with audio fre-quency input signals. The FM RF signal output is in thebroadcast FM band and can be monaural or modulators have been with us since the time ofMajor Edwin H. Armstrong (sometimes known as thefather of FM) and his classic 1936 paper on the first put down on paper the fundamental concept of afixed center frequency that is varied per a constant de-viation ratio that is independent of the frequency of themodulating signal.

2 FM became very popular becausemuch of the noise generated in nature exhibits AM char-acteristics. The signal-to-noise ratio of an FM signal willbe found to exceed that of an AM signal due to the im-provement ratio related to the deviation ratio. We are allfamiliar with the wideband FM broadcast band and itssuperior sound quality and noise immunity when com-pared with AM FM modulators typically employ an oscillatorwith a varactor diode in the tuned circuit. The voltage tothe varactor is varied by the modulating signal, whichchanges its capacitance, therefore changing the reso-nant point of the oscillator s tuned circuit, which shiftsthe frequency.

3 As noted above, constant center fre-quency and deviation ratio are essential to quality work has been done to embellish the basic oscilla-tor circuit to provide the needed stability. Even thoughcomplex circuitry can be added to automatically com-pensate for power supply and temperature variations,these circuits still require periodic recalibration to dealwith component Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 DSP and the AD9850 Direct Digital Synthesizerby Dean R. BeckerRecent developments in digital signal processing (DSP) Devices have made it possible to create high quality FMmodulation using all-digital circuitry.

4 This modulatordoes not require periodic recalibration, it does not driftwith temperature or power supply variations, and it isvery easy to reproduce since there are no Analog adjust-ments (other than the level of the input Analog modulat-ing signal). At the heart of this circuit is a Direct DigitalSynthesizer (DDS), such as the AD9850 Complete-DDS(C-DDS) device. The AD9850 consists of a digital phaseaccumulator, a phase/amplitude converter and a D/Aconverter. It creates a linear ramp in the phase accumu-lator with a frequency that is dependent on the phaseaccumulator s input value.

5 The ramp is mapped to asampled sinusoidal signal by the phase-to-amplitudeconverter. The sampled digital signal is then D/A con-verted and filtered with a reconstruction filter to pro-duce an Analog waveform. All functions of the DDS(except the Analog reconstruction filter) are contained inthe AD9850 chip. The sampled signal is created at asample rate of 125 MHz, allowing high frequency RF out-put. Prior to the release of the AD9850, very fast, inex-pensive C-DDS Devices did not exist. For a more detailedexplanation of the operation and specifications of aC-DDS device, please refer to the theory of operation inthe AD9850 data IMPLEMENTATIONThe implementation of the FM RF generator consists ofan Analog Devices EZ-KIT Lite 16-bit DSP developmentboard, some I/O decode circuitry, and an evaluationboard for the DDS the AD9850-FSPCB as shown inFigure DECODELOGICADSP-2181 DSP mPAD1847 STEREOCODECAUDIO INL AND REZ-KIT LITEADSP-2181 BUS8-BITDATAAD9850/FSPCBDACOUTFM RFOUTPUTLINE INFigure 1.

6 Block Diagram of FM RF Generator Implementation 2 AN-543 The EZ-KIT Lite contains an Analog Devices ADSP-2181KS-133 16-bit DSP with 16K 24 of program memoryRAM and 16K 16 of data memory documentation comes with the EZ-KIT Litedevelopment board and schematics for the AD9850C-DDS are in the AD9850 data sheet. The I/O decodelogic and interconnections are shown in the schematicin Figure AD9850-FSPCB evaluation board is made to inter-face to the parallel port of a PC. It has a Centronics-typeconnector on it and buffers to work with the parallelport.

7 A simple way to connect it to an external DSP is bydisabling the buffers as shown in the schematic, by dis-connecting the output enables from the ground plane ofthe PCB and wiring them to VCC. With the buffers dis-abled, the ADSP-2181 on the EZ-KIT Lite can drive theAD9850 data lines directly. The I/O interface in the sche-matic decodes I/O address 1 to create the W_CLK (writeclock) signal and I/O address 2 to create the FQ_UD (fre-quency update) signal. These are control signals used towrite the consecutive frequency bytes into the AD9850and then strobe the entire 32-bit frequency word into theoperational register respectively.

8 RESET is brought in toinitialize the AD9850. Please refer to the AD9850 datasheet for more information on loading the FIRMWARE IMPLEMENTATIONTwo programs are described here. The first is for a mon-aural FM modulator ( ) and the second is forstereo ( ). Both programs are stand-alonesingle modules and can be loaded into the EZ-KIT Litevia the serial port using the EZ-KIT Lite monitor. Theybegin with codec variable initialization. The only differ-ence here is that the codec sample rate for fm_xmit is48 kHz while it is set to kHz in FmStereo.

9 (This willbe explained with the FmStereo program). This part, theinitialization code, interrupt vectors and DSP and codecinitialization, was copied from a sample program thatcomes with the EZ-KIT Lite. The following partial listingin Figure 3 describes what happens on every inputsample from the codec. First the left and right inputsamples are divided by two to ensure that they do notoverflow as they are summed together. Next, a devia-tion value is multiplied by the previous sum and thenhas a center frequency value added to the product. Thisis all done in 32-bit double precision to preserve the ac-curacy of the C-DDS.

10 Finally, the 32-bit frequency wordis broken into four bytes and sent to the AD9850 INTERFACE BOARD74LS0474LS0474LS04 CUT OE's FROM GNDTHEN TIE TO VCCCONNECT DIRECTLYTO 74AC574 PINSFQUDWCLKRESETVCC74AC57474AC57474LS10 74LS1011J2-41J2-2J2-1J2-39J3-37 IOMSA1 WRA0 RESETEZ-KIT LITEBOARDAD9850-FSPCBEVAL BOARDMODIFIED CONNECTIONSQ1Q2Q3Q4Q5Q6Q7Q81918171615141 312D7D6D5D4D3D2D1D02345678911D1D2D3D4D5D 6D7D8 CLKOEU2Q1Q2Q3Q4Q5Q6Q7Q81918171615141312U 3D1D2D3D4D5D6D7D8 CLKOE23456789111213123456U2A21U2CU2B4365 D15D14D13D12D11D10D9D8P2-30P2-29P2-28P2- 27P2-26P2-25P2-24P2-23 Figure 2. Schematic of I/O Decode Logic and Interconnections 3 ;{ 9850 write clock address }.