AD585 High Speed, Precision Sample-and-Hold …

1 REV. AInformation furnished by analog devices is believed to be accurate andreliable. However, no responsibility is assumed by analog devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of analog Speed, PrecisionSample-and-Hold AmplifierAD585 One Technology Way, Box 9106, Norwood, MA 02062-9106, : 617/329-4700 Fax: 617 ms Acquisition Time to maxLow Droop Rate: mV/ms maxSample/Hold Offset Step: 3 mV maxAperture Jitter: nsExtended Temperature Range.

2 558C to +1258 CInternal Hold CapacitorInternal Application Resistors612 V or 615 V OperationAvailable in Surface MountAPPLICATIONSData Acquisition SystemsData Distribution SystemsAnalog Delay & StoragePeak Amplitude MeasurementsMIL-STD-883 Compliant Versions AvailablePRODUCT DESCRIPTIONThe AD585 is a complete monolithic Sample-and-Hold circuitconsisting of a high performance operational amplifier in serieswith an ultralow leakage analog switch and a FET input inte-grating amplifier. An internal holding capacitor and matchedapplications resistors have been provided for high Precision andapplications performance of the AD585 makes it ideal for high speed10- and 12-bit data acquisition systems, where fast acquisitiontime, low sample-to-hold offset, and low droop are critical.

3 TheAD585 can acquire a signal to in 3 s maximum, andthen hold that signal with a maximum sample-to-hold offset of3 mV and less than 1 mV/ms droop, using the on-chip holdcapacitor. If lower droop is required, it is possible to add alarger external hold high speed analog switch used in the AD585 exhibitsaperture jitter of ns, enabling the device to sample full scale(20 V peak-to-peak) signals at frequencies up to 78 kHz with12-bit AD585 can be used with any user-defined feedback net-work to provide any desired gain in the sample mode. On-chipprecision thin-film resistors can be used to provide gains of +1, 1, or +2.

4 Output impedance in the hold mode is sufficientlylow to maintain an accurate output signal even when driving thedynamic load presented by a successive-approximation A/Dconverter. However, the output is protected against damagefrom accidental short control signal for the HOLD command can be either activehigh or active low. The differential HOLD signal is compatiblewith all logic families, if a suitable reference level is provided. Anon-chip TTL reference level is provided for TTL AD585 is available in three performance grades. The JPgrade is specified for the 0 C to +70 C commercial temperaturerange and packaged in a 20-pin PLCC.

5 The AQ grade is speci-fied for the 25 C to +85 C industrial temperature range and ispackaged in a 14-pin cerdip. The SQ and SE grades are speci-fied for the 55 C to +125 C military temperature range andare packaged in a 14-pin cerdip and 20-pin HIGHLIGHTS1. The fast acquisition time (3 s) and low aperture jitter ( ns) make it the first choice for very high speed dataacquisition The droop rate is only mV/ms so that it may be used inslower high accuracy systems without the loss of The low charge transfer of the analog switch keeps sample-tohold offset below 3 mV with the on-chip 100 pF hold capaci-tor, eliminating the trade-off between acquisition time andS/H offset required with other The AD585 has internal pretrimmed application resistors forapplications The AD585 is complete with an internal hold capacitor forease of use.

6 Capacitance can be added externally to reducethe droop rate when long hold times and high accuracy The AD585 is recommended for use with 10- and 12-bitsuccessive-approximation A/D converters such as AD573,AD574A, AD674A, AD7572 and The AD585 is available in versions compliant with MIL-STD-883. Refer to the analog devices Military Products Databookor current AD585 /883B data sheet for detailed BLOCK DIAGRAM DIP LCC/PLCC PackageAD585 SPECIFICATIONSM odel AD585J AD585A AD585 SMinTypMaxMinTypMaxMinTypMaxUnitsSAMPLE/ HOLD CHARACTERISTICSA cquisition Time, 10 V Step to s 20 V Step to sAperture Time, 20 V p-p Input,HOLD 0 V353535nsAperture Jitter, 20 V p-p Input,HOLD 0 Time, 20 V p-p Input,HOLD 0 V.

7 To sDroop Rate111mV/msDroop Rate TMIN to TMAX Doubles Every 10 C Double Every 10 C Doubles Every 10 CCharge Offset 33 33 33mVFeedthrough20 V p-p, 10 kHz CHARACTERISTICS1 Open Loop GainVOUT = 20 V p-p, RL = 2k200,000200,000200,000V/VApplication Resistor RejectionVCM = 10 V808080dBSmall Signal Gain BandwidthVOUT = 100 mV Power BandwidthVOUT = 20 V p-p160160160kHzSlew RateVOUT = 20 V p-p101010V/ sOutput Resistance (Sample Mode)IOUT = 10 Output Short Circuit Current505050mAOutput Short Circuit Duration Indefinite Indefinite IndefiniteANALOG INPUT CHARACTERISTICSO ffset Voltage522mVOffset Voltage, TMIN to TMAX633mVBias Current222nABias Current, TMIN to TMAX5520502nAInput Capacitance, f = 1 MHz101010pFInput Resistance, Sample or Hold20 V p-p Input, A = +1101210121012 DIGITAL INPUT CHARACTERISTICSTTL Reference Input high VoltageTMIN to Input Low VoltageTMIN to Input Current (Either Input)

8 505050 APOWER SUPPLY CHARACTERISTICSO perating Voltage Range+5, 18+5, 18+5, 18 VSupply Current, RL = 610610610mAPower Supply Rejection, Sample Mode707070dBTEMPERATURE RANGES pecified Performance0+70 25+85 55+125 CPACKAGE OPTIONS3, 4 Cerdip (Q-14) AD585AQ AD585 SQLCC (E-20A) AD585 SEPLCC (P-20A) AD585JP(typical @ +258C and VS = 612 V or 615 V, and CH = Internal, A = +1,HOLD active unless otherwise noted)Specifications subject to change without shown in boldface are tested on all production units at final electricaltest. Results from those tests are used to calculate outgoing quality min and max specifications are guaranteed, although only those shown inboldface are tested on all production input signal is the minimum supply minus a headroom voltage of tested at 55 = Leadless Ceramic Chip Carrier; P = Plastic Leaded Chip Carrier; Q = AD585 /883B specifications, refer to analog devices Military Products A 2 AD585 REV.

9 A 3 Figure 2. Acquisition Time vs. Hold Capacitance(10 V Step to )ABSOLUTE MAXIMUM RATINGSS upplies (+VS, VS) .. 18 VLogic Inputs .. VSAnalog Inputs .. VSRIN, RFB Pins .. VSStorage Temperature .. 65 C to +150 CLead Temperature (Soldering) .. 300 COutput Short Circuit to Ground .. IndefiniteTTL Logic Reference ShortCircuit to Ground .. IndefiniteAD585 REV. A 4 SAMPLED DATA SYSTEMSIn sampled data systems there are a number of limiting factorsin digitizing high frequency signals accurately. Figure 9 showspictorially the Sample-and-Hold errors that are the limiting fac-tors. In the following discussions of error sources the errors willbe divided into the following groups: 1.

10 Sample-to-Hold Transi-tion, 2. Hold Mode and 3. Hold-to-Sample 9. Pictorial Showing Various S/H CharacteristicsSAMPLE-TO-HOLD TRANSITIONThe aperture delay time is the time required for the Sample-and-Hold amplifier to switch from sample to hold. Since this is effec-tively a constant then it may be tuned out. If however, theaperture delay time is not accounted for then errors of the mag-nitude as shown in Figure 10 will 10. Aperture Delay Error vs. FrequencyTo eliminate the aperture delay as an error source the sample-to-hold command may be advanced with respect to the inputsignal .Once the aperture delay time has been eliminated as an errorsource then the aperture jitter which is the variation in aperturedelay time from sample-to-sample remains.