AD9081 and AD9082 Direct RF Sampling Transceivers

1 AD9081 / AD9082 System Development User Guide UG-1578 One Technology Way Box 9106 Norwood, MA 02062-9106, Tel: Fax: AD9081 and AD9082 Direct RF Sampling Transceivers PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 315 SCOPE This user guide provides information for systems engineers and software developers using the AD9081 and AD9082 family of software defined , Direct RF Sampling Transceivers . This family of devices consists of high performance digital-to-analog converters (DAC) and analog-to-digital converters (ADC) with configurable digital datapaths in support of processing signals or RF bands of varying bandwidth. These devices also support various digital features that enhance or simplify system integration.

2 Table 1 outlines the key differences between these devices, and the Common Features section outlines the common features shared among the devices. These devices are interchangeable unless otherwise stated in this user guide. For full specifications on the AD9081 and AD9082 , refer to the AD9081 and AD9082 data sheets, which must be consulted in conjunction with this user guide to achieve successful product selection and design. Table 1. Product Listing with Distinguishing Features1 Device and Channel Configuration Transmit (Tx) Receive (Rx) Special Digital Features Device ID Register Values No. of DAC Channels, Resolution Max DAC Rate (GSPS) Max Tx Channel Bandwidth (GHz) No. of ADC Channels Max ADC Rate (GSPS) Max Rx Channel Bandwidth (GHz) Tx and Rx Bypass Operation Rx to Tx Loopback Fast Frequency Hopping (FFH) Direct Digital Synthesis (DDS)

3 0x003 0x004 0x005 0x006 AD9081 -4D4AC 4 16b 12 4 4 2 Yes Yes Yes Yes 0Fh 81h 90h A3h -4D4AC 4 12b 12 4 4 2 Yes Yes Yes Yes 0Fh 81h 90h A3h -4D4AB 4 16b 12 4 4 Yes Yes Yes Yes 0Fh 81h 90h B3h AD9082 -4D2AC 4 16b 12 2 6 3 Yes Yes Yes Yes 0Fh 82h 90h 23h -4D2AC 4 12b 12 2 6 3 Yes Yes Yes Yes 0Fh 82h 90h 23h -2D2AC 2 16b 12 2 6 3 Yes Yes Yes Yes 0Fh 82h 90h 13h AD9988 -4D4AC 4 16b 12 4 4 No No No No 0Fh 88h 99h A3h AD9986 -4D2AC 4 16b 12 2 6 No No No No 0Fh 86h 99h 23h -4D2AC 2 16b 12 2 6 No No No No 0Fh 86h 99h 23h AD9207 N/A N/A N/A 2 6 3 Yes N/A Yes N/A 03h 07h 92h 23h AD9209 N/A N/A N/A 4 4 2 Yes N/A Yes N/A 03h 09h 92h A3h AD9177 4 16b 12 N/A N/A N/A Yes Yes Yes Yes 04h 77h 91h A3h 1 N/A means not applicable.

4 UG-1578 AD9081 / AD9082 System Development User Guide Rev. 0 | Page 2 of 315 TABLE OF CONTENTS Scope .. 1 System Overview .. 6 Common Features .. 6 Analog Features .. 6 Digital Features .. 6 SERDES Interface .. 6 software 9 software Architecture .. 9 Folder Structure .. 9 /src/ad9081_api .. 9 /src/ad9081_api/adi_inc .. 9 /src/ad9081_ 9 /src/ad9081_api/ AD9081 .. 9 /src/ad9081_app .. 10 /doc .. 10 API Integration and Build .. 10 Integrating the AD9xxx API Into an Application .. 10 API Overview Block Diagram .. 12 Serial Peripheral Interface .. 14 SPI Configuration API .. 14 Sampling Clock and Distribution Options .. 16 Clock Multiplier .. 16 Clock Receiver Input .. 18 Clock Output Driver .. 20 Clock Configuration APIs .. 20 JESD204B/C Interface Functional Overview and Common Requirements.

5 21 New Features in the JESD204C Standard .. 21 Terminology and Parameters .. 21 Physical Layer Updates .. 22 Transport and Link Layer .. 22 Multiblocks (MB) and Extended Multiblocks (EMB) .. 22 Synchronization Word .. 24 CRC-12 Encoder .. 24 8-Bit/10-Bit Link Establishment Overview .. 24 64-Bit/66-Bit Link Establishment Overview .. 24 SERDES PLL and 24 SERDES PLL Configuration API .. 25 SYSREF and Subclass 1 Operation .. 26 SYSREF Receiver Input and Interface Options .. 27 SYSREF Modes .. 28 SYSREF Monitor 28 SYSREF Error Window .. 28 SYSREF Sampling Modes .. 29 SYSREF Setup/Sync Procedure .. 30 SYSREF Phase Adjust .. 31 SYSREF Configuration APIs .. 31 Receive Input and Digital Datapath .. 34 ADC Architecture Overview .. 34 Calibration and Specifying Nyquist Zone .. 34 ADC Input Buffer.

6 35 ADC Input Buffer API .. 36 Overload Protection .. 36 ADC Input Driving Considerations .. 37 Receive Digital Datapath Overview .. 38 Receive Data Path Configuration Considerations .. 39 Receive Datapath Configuration API .. 40 Mux0 .. 40 MUX0 Configuration API .. 41 Bypassable Integer Delay and PFILT .. 41 Integer Delay and PFILT Configuration API .. 42 Mux1 .. 42 Mux1 Configuration API .. 42 Receive Main Digital Datapath .. 43 Main Data Path CDDC .. 43 CDDC Variable IF NCO Operating Modes .. 45 CDDC NCO Synchronization Options .. 46 NCO Setting Consideration for Homodyne Transmit-to-Receive Loopback Applications.. 47 NCO Dual Modulus Mode .. 47 NCO Integer-N Mode .. 48 Optional Fractional Delay for Receive Main Datapath 0 or Receive Main Datapath 3 Only .. 48 Main Datapath Decimation Stage.

7 49 Bypassable 6 dB Gain Stage and Complex to Real Conversion .. 49 Mux2 .. 50 Receive Channelizer Digital Datapath .. 51 Receive Channelizer Fine Digital Downconverter .. 51 FDDC Variable IF NCO Operating Modes .. 51 NCO Synchronization Options for FDDC .. 53 AD9081 / AD9082 System Development User Guide UG-1578 Rev. 0 | Page 3 of 315 NCO Dual Modulus Mode for FDDC .. 53 NCO Integer-N Mode for FDDC .. 53 Receive Channelizer Decimation Stage .. 53 Bypassable 6 dB Gain Stage and C2R Conversion .. 54 Upsampler .. 55 MUX3 (Data Format and Selection) .. 55 Mux4 (JESD204B/C Transmitter JESD Data Router) .. 56 JESD204B/C 57 Functional Overview .. 57 JESD204B/C Transmitter Clock Relationships .. 58 Transport Layer .. 58 Data Link Layer Selection, Selecting the Encode Scheme . 58 8-Bit/10-Bit Link Layer.

8 58 64-Bit/66-Bit Link Layer and Link Establishment .. 60 JESD204B/C Transmitter Physical Layer .. 61 ADC Path Deterministic Latency .. 66 JESD204B/C Transmitter Multichip Synchronization .. 68 Configuring the JESD204B/C Transmitter Link .. 69 high Level Configuration 69 JESD204B/C Transmitter Configuration API .. 69 JESD204B/C Transmitter Mode 76 Transmit Digital Data Path and Output .. 111 JESD204B/C Receiver Functional Overview .. 111 JESD204B/C Receiver Clock Relationships .. 111 Physical Layer .. 111 Data Link Layer .. 114 JESD204C Receiver 64-bit/66-bit Link Layer .. 123 DAC Path Deterministic Latency .. 125 JESD204B/C Receiver Multichip Synchronization .. 128 JESD204B/C Receiver Transport Layer .. 129 JESD204B/C Receive Mode Tables .. 129 Configuring the JESD204B/C Receiver.

9 132 high Level Configuration 132 JESD204B/C Receiver Configuration API .. 132 Transmit Path and JESD204B/C Receiver API Functions .. 133 Transmit Digital Datapath Overview .. 134 Total Datapath Interpolation .. 135 Data Router Multiplexers and Default 136 4 4 Crossbar .. 136 Channelizer Data Path .. 137 Digital Gain .. 137 Skew Adjust .. 138 Channelizer Interpolation Stage .. 138 Channelizer FDUC .. 138 FDUC Dual Modulus NCO Mode .. 139 Channelizer NCO Only Mode .. 140 8 8 Crossbar Multiplexer .. 140 Main Digital Datapath .. 141 Digital Gain Scaling .. 142 Main Datapath Interpolation Stage .. 142 Main Datapath CDUC .. 143 CDUC NCO Synchronization and Reset .. 144 CDUC Dual-Modulus NCO Mode .. 144 CDUC Integer NCO Mode and Phase Offset .. 144 Main Path NCO Only Mode .. 144 Optional Calibration NCO.

10 144 Modulator Multiplexer (Mod Mux) .. 145 DAC Outputs .. 149 DAC Outputs API .. 150 DAC Output Impedance Characteristics .. 150 DC-Coupled Operation .. 151 MSB Shuffle .. 151 MSB Rotation .. 152 Auxiliary Features .. 153 Receive AGC Assist Functions .. 153 Fast Detect Mode Configuration Examples .. 154 Signal Monitor Block .. 155 Programmable Filter (PFILT) .. 157 Supported Modes in the AD9082 .. 159 Supported Modes in the AD9081 .. 160 Use Case Scenarios to Filter Modes Mapping .. 161 Programmable Gain Scaling .. 161 Coefficient Bank Description and Fast Updating Between Coefficient Banks .. 162 Coefficient Size Optimizations .. 163 SPI Programming of 163 Transmit Downstream Power Amplifier Protection .. 165 Power Detection and Protection (PDP) Block .. 166 JESD Interface and Synchronization Error Protection.