ADC12D1620QMP-SP 12-Bit, Single or Dual, 3200- …

1 Product Order Technical Tools & Support &. Folder Now Documents Software Community ADC12D1620 QML-SP. SNAS717 APRIL 2017. ADC12D1620 QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC). 1 Features 3 Description . 1 Total Ionizing Dose (TID) to 300 krad(Si) The ADC12D1620 QML device uses a package redesign to achieve better ENOB, SNR, and X-talk Single Event Functional Interrupt (SEFI) Tested compared to the ADC12D1600 QML. As is its Single Event Latch-up (SEL) > 120 MeV-cm2/mg predecessor, the ADC12D1620 QML is a low-power, Cold Sparing Capable high-performance CMOS analog-to-digital converter Wide Temperature Range 55 C to +125 C (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to GSPS in an interleaved Power Consumption = W or W (1600- or mode. It can also be used as a dual-channel ADC for 800-MHz Clock) sampling rates up to GSPS.

2 For sampling rates 3-dB Input Bandwidth = 3 GHz below 800 MHz, there is a low-sampling power- Low-Sampling Power-Saving Mode (LSPSM) saving mode (LSPSM) that reduces power consumption to less than W per channel (typical). Reduces Power Consumption and Improves The ADC can support conversion rates as low as 200. Performance for fCLK 800 MHz MSPS. Auto-Sync Function for Multi-Chip Systems Time Stamp Feature to Capture External Trigger Device Information(1). Test Patterns at Output for System Debug PART NUMBER GRADE PACKAGE. 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed ADC12D1620 CCMLS Flight 300 krad CCGA (376). LVDS Outputs Pre-flight engineering ADC12D1620 CCMPR CCGA (376). prototype Single Power Supply Daisy chain, mechanical ADC10D1000 DAISY CCGA (376). sample, no die 2 Applications ADC12D1620 LGMLS Flight 300 krad CLGA (256). Direct RF Down Conversion Pre-flight engineering ADC12D1620 LGMPR CLGA (256).

3 Prototype Satellite Wideband Communications Daisy chain, mechanical Synthetic Aperture RADAR and LIDAR ADC10D1000 LDAZ. sample, no die CLGA (256). (1) For all available packages, see the package orderable addendum (POA) at the end of the data sheet. space Functional Block Diagram 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC12D1620 QML-SP. SNAS717 APRIL 2017 Table of Contents 1 Features .. 1 Timing Diagrams .. 27. 2 Applications .. 1 Typical Characteristics .. 32. 3 Description .. 1 7 Detailed Description .. 37. 4 Revision 2 Overview .. 37. Functional Block Diagram .. 37. 5 Pin Configuration and Functions .. 3. Feature 38. 6 12. Device Functional 46. Absolute Maximum Ratings.

4 12. Programming .. 47. ESD 12. Register Maps .. 52. Recommended Operating 12. Thermal Information .. 13 8 Application and Implementation .. 59. Application 59. Converter Electrical Characteristics: Static Converter Characteristics .. 13 Radiation Environments .. 66. Converter Electrical Characteristics: Dynamic Cold Sparing .. 66. Converter 15 9 Power Supply 68. Converter Electrical Characteristics: Analog System Power-On 68. Input/Output and Reference 17. 10 69. Converter Electrical Characteristic: Channel-to- Layout Guidelines .. 69. Channel 18. Layout Example .. 71. Converter Electrical Characteristics: LVDS CLK Input Characteristics .. 18 Thermal Considerations .. 73. Electrical Characteristics: AutoSync 19 Board Mounting Recommendation .. 73. Converter Electrical Characteristics: Digital Control 11 Device and Documentation Support.

5 75. and Output Pin Characteristics .. 19 Device Support .. 75. Converter Electrical Characteristics: Power Supply Receiving Notification of Documentation Updates 77. Characteristics .. 21 Community 77. Converter Electrical Characteristics: AC Electrical Trademarks .. 77. Characteristics .. 23. Electrostatic Discharge Caution .. 77. Electrical Characteristics: Delta 24. Glossary .. 77. Timing Requirements: Serial Port Interface .. 25. 12 Mechanical, Packaging, and Orderable Timing Requirements: 26. Information .. 77. Quality Conformance Inspection .. 26. Engineering Samples .. 78. 4 Revision History DATE REVISION NOTES. April 2017 * Initial release 2 Submit Documentation Feedback Copyright 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620 QML-SP. ADC12D1620 QML-SP. SNAS717 APRIL 2017. 5 Pin Configuration and Functions The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance.

6 See Layout Guidelines for more information. NAA Package 376-Pin CCGA and CLGA. Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20. A G ND V _A S DO T PM NDM V _A G ND V _E G ND_E DId 0+ V _DR DId 3+ G ND_DR DId 6+ V _DR DId 9+ G ND_DR DId 11+ DId 11- G ND_DR A. B V bg G ND E CE b S DI CalRu n V _A G ND G ND_E V _E DId 0- DId 2+ DId 3- DId 5+ DId 6- DId 8+ DId 9- DId 10+ DI0+ DI1+ DI1- B. C Rtrim + V cm o Rext+ S CS b S CL K G ND V _A V _E G ND_E DId 1+ DId 2- DId 4+ DId 5- DId 7+ DId 8- DId 10- DI0- V _DR DI2+ DI2- C. D V _A Rtrim - Rext- G ND G ND CAL V b iasI V _A V _A DId 1- V _DR DId 4- G ND_DR DId 7- V _DR G ND_DR V _DR DI3+ DI4+ DI4- D. E V _A T d iod e+ RS V 1 G ND. 1 2 3 4 5 6 7 8 9 10 11. G ND_DR DI3- DI5+ DI5- E. F V _A G ND_T C T d iod e- RS V 2. AA GND GND GND GND GND GND GND GND GND GND G ND_DR DI6+ DI6- G ND_DR F. G V _T C G ND_T C V _T C V _T C AB GND GND GND GND GND GND GND GND GND GND GND DI7+ DI7- DI8+ DI8- G.

7 AC GND GND GND GND GND GND GND GND GND GND GND. H V in I+ V _T C G ND_T C V _A DI9+ DI9- DI10+ DI10- H. AD GND GND GND GND GND GND GND GND GND GND GND. J V in I- G ND_T C V _T C V b iasI V _DR DI11+ DI11- V _DR J. AE GND GND GND GND GND GND GND GND GND GND GND. K G ND V b iasI V _T C G ND_T C O RI+ O RI- DCL KI+ DCL KI- K. AF GND GND GND GND GND GND GND GND GND GND GND. L G ND V b iasQ V _T C G ND_T C O RQ + O RQ - DCL KQ + DCL KQ - L. AG GND GND GND GND GND GND GND GND GND GND GND. M V in Q - G ND_T C V _T C V b iasQ G ND_DR DQ 11+ DQ 11- G ND_DR M. AH GND GND GND GND GND GND GND GND GND GND GND. N V in Q + V _T C G ND_T C V _A DQ 9+ DQ 9- DQ 10+ DQ 10- N. AJ GND GND GND GND GND GND GND GND GND GND GND. P V _T C G ND_T C V _T C V _T C. AK GND GND GND GND GND GND GND GND GND GND GND. DQ 7+ DQ 7- DQ 8+ DQ 8- P. R V _A G ND_T C V _T C V _T C AL GND GND GND GND GND GND GND GND GND GND GND V _DR DQ 6+ DQ 6- V _DR R.

8 T V _A G ND_T C G ND_T C G ND V _DR DQ 3- DQ 5+ DQ 5- T. U G ND_T C CL K+ P DI G ND G ND RCO u t1- V b iasQ V _A V _A DQ d 1- V _DR DQ d 4- G ND_DR DQ d 7- V _DR V _DR G ND_DR DQ 3+ DQ 4+ DQ 4- U. DCL K_R. V CL K- ST +. P DQ LS P S M DE S RCO u t2+ RCO u t2- V _E G ND_E DQ d 1+ DQ d 2- DQ d 4+ DQ d 5- DQ d 7+ DQ d 8- DQ d 10- DQ 0- G ND_DR DQ 2+ DQ 2- V. DCL K_R. W ST - G ND RS V DDRP h RCL K- V _A G ND G ND_E V _E DQ d 0- DQ d 2+ DQ d 3- DQ d 5+ DQ d 6- DQ d 8+ DQ d 9- DQ d 10+ DQ 0+ DQ 1+ DQ 1- W. Y G ND V _A FS R RCL K+ RCO u t1+ V _A G ND V _E G ND_E DQ d 0+ V _DR DQ d 3+ G ND_DR DQ d 6+ V _DR DQ d 9+ G ND_DR DQ d 11+ DQ d 11- G ND_DR Y. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20. The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Layout Guidelines for more information.

9 Copyright 2017, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: ADC12D1620 QML-SP. ADC12D1620 QML-SP. SNAS717 APRIL 2017 Pin Functions: Analog Front-End and Clock Pins PIN. TYPE DESCRIPTION EQUIVALENT CIRCUIT. NAME NO. ANALOG FRONT-END AND CLOCK PINS. VA. Differential converter sampling clock. In the non- DES mode, the analog inputs are sampled on the CLK+ positive transitions of this clock signal. In the DES AGND 50k U2/V1 I. CLK mode, the selected input is sampled on both 100 VBIAS. VA. transitions of this clock. This clock must be AC- 50k coupled. AGND. VA. Differential DCLK reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ. outputs of two or more ADC12D1620 devices in order to synchronize them with other ADC12D1620. devices in the system. DCLKI and DCLKQ are DCLK_RST+ always in phase with each other, unless one AGND.

10 V2/W1 I. DCLK_RST channel is powered down, and do not require a 100. pulse from DCLK_RST to become synchronized. VA. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync. AGND. VA. Reference clock input. When the AutoSync feature is active, and the ADC12D1620 is in slave mode, the internal divided clocks are synchronized with RCLK+ respect to this input clock. The delay on this clock AGND 50k Y4/W5 I. RCLK may be adjusted when synchronizing multiple ADCs. 100 VBIAS. VA. This feature is available in ECM with the DRC bits of 50k the AutoSync Control Register (Addr: Eh, Bits: 15:7). AGND. VA. Reference clock output 1 and 2. These signals, when enabled, provide a reference clock. The RCOut rates for all of the available modes can be found in Table 8; the rates displayed in the table are independent of whether the ADC is in master or slave mode.