ADE9000 Technical Reference Manual (Rev. 0)

1 ADE9000 Technical Reference Manual UG-1098 One Technology Way P. O . Box 9106 Norwood, MA 02062-9106, Tel: Fax: Functionality and Features of the ADE9000 High Performance, Multiphase Energy and Power Quality Monitoring IC PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 86 SCOPE This Reference Manual provides a detailed description of the ADE9000 functionality and features. This document must be used in conjunction with the ADE9000 data sheet. FUNCTIONAL BLOCK DIAGRAM CF1CF2 DIGITAL BLOCKSINC + DECIMATIONDSP ENGINETOTAL AND FUNDAMENTAL:{ IRMS, VRMS, ACTIVE,REACTIVE,APPARENT POWERAND ENERGY }VTHD, ITHD, FREQUENCY,PHASE ANGLE,POWER FACTOR, VPEAK, IPEAK, DIP,SWELL, OVERCURRENT,FAST RMS,10/12 CYCLE RMS, PHASE SEQ ERRORSARTEMPSENSORSPIINTERFACECLKINCLKOU TSCLKMISOMOSICSGNDIAPIANVAPVANADCPGAADCP GAADE9000 ADCPGAADCPGAADCPGAADCPGARESAMPLINGENGINE WAVEFFORM BUFFER(32ksps, 8kspsADC SAMPLESOR RESAMPLED DATA)USER ACCESSIBLEREGISTERSDIGITAL TOFREQUENCYCONVERSION (CF)CF3/ZXCF4/ TOFREQUENCYCONVERSION(CF)15523-001 Figure 1.

2 UG-1098 ADE9000 Technical Reference Manual Rev. 0 | Page 2 of 86 TABLE OF CONTENTS Scope .. 1 Functional Block Diagram .. 1 Revision History .. 2 Analog-to-Digital Converter (ADC) .. 3 Overview .. 3 Analog Input Configuration .. 3 Internal RF Immunity Filter .. 4 Modes of Operation .. 4 Output Data Rates and Format .. 4 Voltage Reference .. 5 Crystal Oscillator/External Clock .. 6 Power Management .. 7 Power Modes .. 7 Power-On Sequence .. 7 Brownout Detection .. 8 Reset .. 8 Changing Power Modes .. 8 Measurements .. 9 Current Channel Measurement Update Rates .. 9 Full-Scale Codes .. 13 Power and Filter-Based RMS Measurement Algorithms .. 13 Energy Measurements Overview .. 17 Energy Accumulation .. 18 Power Accumulation .. 23 Power Quality Measurements .. 24 Temperature .. 31 Accessing On-Chip Data.

3 32 SPI Protocol Overview .. 32 SPI Wr it e .. 33 SPI Read .. 33 SPI Burst Read .. 33 SPI Protocol CRC .. 34 Additional Communication Verification Registers .. 34 CRC of Configuration 35 Waveform Buffer .. 36 Fixed Data Rate Waveforms .. 36 Fixed Data Rate Waveforms Filling and Trigger-Based Modes .. 37 Resampled Waveforms .. 39 Configuring the Waveform Buffer .. 40 Burst Read Waveform Buffer Samples from SPI .. 40 Interrupts/EVENT .. 43 Interrupts (IRQ0 and IRQ1) .. 43 43 Status Bits in Additional Registers .. 43 Applying the ADE9000 to Different Metering Configurations .. 44 Non-Blondel Compliant Meters .. 45 Applying the ADE9000 to a 4-Wire Wye Service .. 46 Applying the ADE9000 to a 3-Wire Delta Service .. 47 Applying the ADE9000 to a Non-Blondel Compliant 4-Wire Wye Service .. 48 Applying the ADE9000 to a Non-Blondel Compliant 4-Wire Delta Service.

4 48 ADE9000 Service Type Summary .. 48 Quick Start .. 50 Calibration .. 51 System Parameters .. 51 RMS Calibration .. 51 Phase Calibration .. 51 Power Calibration .. 52 Conversion 52 Register Information .. 53 Register Details .. 65 REVISION HISTORY 3/2017 Revision 0: Initial Version ADE9000 Technical Reference Manual UG-1098 Rev. 0 | Page 3 of 86 ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW The ADE9000 incorporates seven independent, second-order, - ADCs that sample simultaneously. Each ADC is 24 bits and supports fully differential and pseudo differential inputs, which can go above and below ground. The ADE9000 includes a low noise, low drift, internal band gap Reference . Set the EXT_REF bit in the CONFIG1 register if using an external voltage Reference . Each ADC contains a programmable gain amplifier which allows a gain of 1, 2, or 4.

5 ANALOG INPUT CONFIGURATION There is no internal buffering; the impedance of the ADE9000 depends on the programmable gain selected. Fully Differential Inputs The input signals on the IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN, VBP, VBN, VCP, and VCN pins must not exceed V. The differential full-scale input range of the ADCs is 1 V peak ( V rms). Figure 2 and Figure 3 show two common types of input signals for an energy monitoring application. Figure 2 shows the maximum input allowed with differential antiphase signals. A current transformer with center tapped burden resistor generates differential, antiphase signals. Figure 3 shows the maximum input signal with pseudo differential signals, similar to those obtained when sensing the mains voltage signal through a resistive divider or using a Rogowski coil current sensor.

6 The following conditions must be met for the input signals with gain = 1: |IAP, IAN, IBP, IBN, ICP,ICN, VAP, VAN, VBP, VBN, VCP, and VCN| + V peak |IxP IxN| +1 V peak, |VxP VxN| +1 V peak Each ADC contains a programmable gain amplifier which allows a gain of 1, 2, or 4. The ADC produces full-scale output codes with an input of 1 V. With a gain of 1, this full-scale output corresponds to a differential antiphase input of V rms, as shown in Figure 2. At a gain of 2, full-scale output codes are produced with an input of V rms, as shown in Figure 3. At gain of 4, full-scale output codes are generated with a V rms input signal. Note that the voltages on the xP and xN pins must be within V, as specified in the data sheet. Write the x_GAIN bits in the PGA_GAIN register to configure the gain for each channel.

7 + + 44AD =NOTES1. x_PCF IS THE INSTANTANEOUSWAVEFORM OBTAINEDAFTER GAINAND PHASE COMPENSATION.+74,532,0130xFB8E BB53 = 74,532,013 CHANNEL (x_PCF)WAVEFORMDATA RANGE WITH x_GAIN = 1xP INPUT PINxM INPUT PIN+ + Figure 2. Maximum Input Signal with Differential Antiphase Input with Common Mode Voltage = V, Gain = 1 + + + 44AD =+74,532,0130xFB8E BB53 = 74,532,013 CHANNEL (x_PCF)WAVEFORMDATA RANGE WITH x_GAIN = 2xP INPUT PINxM INPUT PINNOTES1. x_PCF IS THE INSTANTANEOUSWAVEFORM OBTAINEDAFTER GAINAND PHASE Figure 3. Maximum Input Signal with Pseudo Differential Input with Common Mode Voltage = V, Gain = 2 UG-1098 ADE9000 Technical Reference Manual Rev. 0 | Page 4 of 86 Interfacing to Current and Voltage Sensors Figure 4 and Figure 6 show the recommended circuits to connect to current transformer sand Rogowski coil current sensors.

8 Figure 5 shows the interface circuit to measure the mains voltage. The antialiasing filter corner is chosen around 7 kHz to provide sufficient attenuation of out of band signals near the modulator clock frequency. The same RC filter corner is used on voltage channels as well, to avoid phase errors between current and voltage signals. Note that the Rogowski coil input network has a second-order antialias filter to further reduce out of band noise because the Rogowski sensor has a 1/f response. 1k maxCTIRb21k 22nFAGND15523-004 Figure 4. Application Circuit with Current Transformer Current Sensor 1M 1k rms240V rms1k 22nFNEUTRALPHASEAGND15523-005 Figure 5. Application Circuit with Voltage Sensed Through Resistor Divider 1k rms22nF22nF100 1k 22nF22nF100 15523-006 Figure 6. Application Circuit with Rogowski Coil Current Sensor INTERNAL RF IMMUNITY FILTER Energy metering applications require the meter to be immune to external radio frequency fields of 30 V/m, from 80 MHz up to 10 GHz, according to IEC 61000-4-3.

9 The ADE9000 has internal antialiasing filters to improve performance in this testing because it is difficult to filter these signals externally. The second-order, internal low-pass filter (LPF) has a corner frequency of 10 MHz. Note that external antialias filters are required to attenuate frequencies above 7 kHz, as shown in the Interfacing to Current and Voltage Sensors section. MODES OF OPERATION Each ADC has two modes of operation: normal mode and disabled mode. In the normal mode of operation, ADCs are turned on and sample continuously. The CHNL_DIS register can be used to disable the ADCs individually. There are 2 different power modes available in the ADE9000 (see the Power Modes section). All ADCs are turned on in PSM0 power mode. In PSM3 mode, all ADCs are disabled and cannot be turned on. Table 1.

10 ADC Operation in PSMx Power Modes PSMx Power Mode ADC Mode of Operation PSM0 Normal (on) PSM3 Disabled (always off ) OUTPUT DATA RATES AND FORMAT When a conversion has been completed, the DREADY bit of the STATUS0 register is set to 1. If the CF4_CFG[3:2] bits in the CONFIG1 register are equal to 11, the CF4/EVENT/DREADY pin corresponds to DREADY and pulses high to indicate when seven new ADC results are ready. In the ADE9000 , the modulator sampling rate (MODCLK) is fixed at MHz (CLKIN/12 = ). The output data rate of the sinc filter is MODCLK/64, whereas the low-pass filter/decimator stage yields an output rate 4 times slower than the sinc filter output rate. Figure 7 shows the digital filtering that takes the MHz ADC samples and creates waveform information at a decimated rate of 32 kHz or 8 kHz.