ADRV9026 System Development User Guide (Rev. PrA)

1 ADRV9026 /ADRV9029 System Development User Guide UG-1727 One Technology Way P. O . Box 9106 Norwood, MA 02062-9106, Tel: Fax: ADRV9026 /ADRV9029 Integrated quad RF transceiver with observation path PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 336 SCOPE This user Guide is the main source of information for System engineers and software developers using the analog devices , Inc., ADRV902x family of software defined radio transceivers. This family consists of the ADRV9026 integrated quad RF transceiver and the ADRV9029 integrated quad RF transceiver with digital predistortion (DPD) and crest factor reduction (CFR) capability. The content of the user Guide covers all functions that are common to both devices and some that are unique to the ADRV9029 device.

2 Throughout the user Guide , the term transceiver is used with functions that are common to both devices . Functions that are unique to the ADRV9029 device use ADRV9029 in the description. This user Guide must be used in conjunction with the product data sheets to incorporate all necessary specifications and descriptions when designing these devices into new equipment. UG-1727 ADRV9026 /ADRV9029 System Development User Guide Rev. 0 | Page 2 of 336 TABLE OF CONTENTS Scope .. 1 Revision History .. 4 System Overview .. 5 System Architecture Description .. 6 Software Architecture .. 6 API Folder Structure .. 6 Private vs. Public API functions .. 7 Hardware Abstraction Layer .. 8 Software Integration .. 10 Software Integration Process Overview .. 10 Software Package Folder Structure Overview.

3 10 API Software Architecture .. 11 Implementing Hardware Abstraction Interface .. 11 Developing the Application .. 11 Serial Peripheral Interface (SPI) .. 20 SPI Bus Signals .. 20 SPI Data Transfer Protocol .. 20 SPI Configuration Using API Function .. 21 Timing 22 System Initialization .. 24 Initialization 24 Serializer/Deserializer (SERDES) Interface .. 25 JESD204B and JESD204C Standard .. 25 Differences Between JESD204B and JESD204C .. 26 Clock Distribution .. 26 Receiver (ADC) Datapath .. 26 Transmitter (DAC) Datapath .. 37 Supported Deframer Link Parameters .. 38 API Software Integration .. 48 Implementation Recommendations .. 48 Link Initialization and Debugging .. 49 First Time System Bring Up Checking Link Integrity .. 49 Sample Iron Python Code for PRBS Testing.

4 49 PRBS Errors .. 50 Static Phase Offset (SPO) TEST to Verify Eye Width .. 51 Checking JESD204C Link Status .. 58 Selecting the Optimal LMFC and LEMC Offset for a Deframer .. 58 Synthesizer Configuration .. 69 Overview .. 69 Connections for External Reference Clock (DEVCLK) .. 69 External Reference Clock (DEVCLK) Requirements .. 70 Clock Synthesizer .. 72 RF Synthesizer .. 72 Auxiliary Synthesizer .. 73 Setting the LO Frequencies .. 73 RF PLL Phase Synchronization .. 76 ARM Processor and Device Calibrations .. 80 ARM State Machine Overview .. 80 System 80 Pre-MCS initialization .. 80 Post-MCS initialization .. 81 Device Calibrations .. 81 Initial Calibrations .. 82 System Considerations for Initial Calibrations .. 85 Tracking Calibrations .. 89 Calibration Guidelines after PLL Frequency Changes.

5 93 Initialization Calibrations to Be Run after Device Initialization .. 103 Tracking Calibration Timing .. 103 ARM Memory Dump .. 103 Stream Processor and System Control .. 105 Slice Stream Processors .. 105 System Control .. 105 Use Cases .. 113 Transmitter Overview and path Control .. 120 API Commands .. 120 DAC Full Scale Function (DAC Boost) .. 125 adi_adrv9025_TxChannelCfg API Structure .. 127 Transmitter Power Amplifier Protection .. 128 PA Protection Description .. 128 Receiver Gain Control and Gain Compensation .. 135 Overview .. 135 Receiver DataPath .. 135 Manual Gain Control (MGC) .. 137 Automatic Gain Control .. 139 ADRV9026 /ADRV9029 System Development User Guide UG-1727 Rev. 0 | Page 3 of 336 AGC Clock and Gain Block Timing .. 147 analog Peak Detector (APD).

6 148 Half-Band 2 Peak Detector .. 149 Power Detector .. 151 API Programming .. 152 AGC Holdover Function .. 153 Receiver Gain Mode Switching Using GPIO .. 153 Gain Control Data Structures .. 155 Sample Python Script Peak Detect Mode with Fast Attack .. 159 Gain Compensation, Floating Point Formatter and Slicer . 162 Receiver Data Format Data Structure .. 168 Digital Filter Configuration .. 172 Overview .. 172 Receiver Signal path .. 172 Complex Low IF to Zero IF .. 173 Complex Low IF to Real IF .. 174 Zero IF to Real IF .. 174 Dual Band Mode .. 174 Dual Band Mode (Real IF) .. 174 HB Filter Only Mode .. 174 Receiver Signal path Example .. 175 Receiver Filter API Structure .. 176 Transmitter Signal path .. 178 Transmit Signal path Example .. 180 Transmitter Filter API Structure.

7 181 observation Receivers Signal path .. 181 observation Receiver Signal path 183 observation Receiver Filter API Structure .. 184 Dual Band Overview: Dual-Band 2T2R Solution .. 185 Dual-Band Configuration and Example Use Cases .. 186 GPIO Configuration .. 188 Digital GPIO Operation .. 188 GPIO_ANA 195 General-Purpose Interrupt (GPINT) .. 197 PLL GPINT Sources .. 198 JESD204B and JESD204C GPINT Sources .. 199 Power Amplifier Protection GPINT Sources .. 199 ARM GPINT Sources .. 200 Stream Processor Sources .. 200 Memory ECC Error .. 200 Software Procedures for GPINT .. 200 API Commands for GPINT .. 201 Auxiliary Converters and Temperature Sensor .. 203 Auxiliary DAC (AUXDAC) .. 203 Auxiliary ADC (AUXADC) .. 205 Temperature Sensor .. 207 SPI2 Description.

8 208 SPI2 Configuration .. 208 Transmitter Control with SPI2 .. 208 Receiver and observation Receiver Control with SPI2 .. 210 RF Port Interface Overview .. 212 RF Port Impedance Data .. 212 ADS Setup Using Data Access Component and SEDZ File 215 Transmitter Bias and Port 216 General Receiver path Interface .. 217 Impedance Matching Network Examples .. 218 Matching Component Recommendations .. 219 Power Management Considerations .. 222 Supply Capacity .. 222 Power Supply Sequence .. 222 Power Supply Domain Connections .. 222 Power Supply Architecture .. 226 Current Consumption .. 226 PCB Layout Considerations .. 228 Overview .. 228 PCB Material and Stack Up Selection .. 228 Fanout and Trace Spacing Guidelines .. 231 Component Placement and Routing Guidelines.

9 231 RF and JESD Transmission Line Layout .. 233 Isolation Techniques .. 237 Power Management Layout Design .. 239 analog Signal Routing Considerations .. 245 Digital Signal Routing Considerations .. 246 Unused Pin Instructions .. 247 transceiver Evaluation Software (TES) Operation .. 248 Initial Setup .. 248 Hardware Kit .. 248 Requirements .. 248 UG-1727 ADRV9026 /ADRV9029 System Development User Guide Rev. 0 | Page 4 of 336 Hardware Setup .. 249 Hardware Operation .. 251 TES Installation .. 251 Starting the transceiver Evaluation Software .. 252 Normal Operation .. 253 Transmitter Operation .. 258 Receiver 260 Scripting .. 261 C Code Generation .. 263 NCO Setup .. 264 Digital Front End Tab Setup .. 265 Digital Predistortion (DPD) .. 268 DFE System Level Overview.

10 268 DPD Introduction and Principle of Operation .. 269 transceiver DPD Overview .. 270 DPD Algorithm Overview .. 273 Initializing Precalibrated Coefficients During Startup .. 276 DPD Sample Capture .. 278 DPD Dynamics .. 281 DPD Regularization .. 284 DPD Robustness .. 286 DPD Actuator Gain Monitoring for Robustness .. 289 DPD Actuator Bypass .. 293 DPD STAT U S .. 294 Recommended Sequence for Enabling the DPD Tracking Calibration .. 294 DPD Stability Metrics Characterization .. 295 DPD Characterization for Optimizing the M Threshold .. 298 Setting Up the DPD Using the GUI .. 298 Crest Factor Reduction (CFR) .. 303 CFR Algorithm Overview .. 305 Overview of Blocks Used in CFR .. 306 API Software 306 Typical Procedure to Set Up CFR Using the GUI.