Advantiv ADV7611 HDMI Receiver Functionality …

1 ADV7611 Reference ManualUG-180 One Technology Way P. O . Box 9106 Norwood, MA 02062-9106, Te l : Fax: Advantiv ADV7611 hdmi Receiver Functionality and Features PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. D | Page 1 of 184 SCOPE This user guide provides a detailed description of the Advantiv ADV7611 hdmi Receiver Functionality and features. DISCLAIMER Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. FUNCTIONAL BLOCK DIAGRAM ADV761109238-001 DPLLCECCONTROLLER5V DETECTAND HPDCONTROLLERCONTROLINTERFACEI2 CXTALPP0 TO P7P8 TO P15 APP16 TO P23 LLCLRCLKSCLK/INT2*MCLK/INT2*HSVS/FIELD/A LSBDEINT1 INT2*XTALNRXA_5 VHPA_A/INT2*EDIDREPEATERCONTROLLERPLLEQU ALIZEREQUALIZERHDCPENGINEHDCPEEPROMDATAP REPROCESSORAND COLORSPACECONVERSIONCOMPONENTPROCESSORBA CKENDCOLOR SPACECONVERSIONPACKETPROCESSORPACKET/INF OFRAMEMEMORYHDMIPROCESSORDDCA_SDADDCA_SC LRXA_0 RXA_2 RXA_1 SCLSDACECRXA_C CONTROLAND DATAABCAUDIO OUTPUT FORMATTEROUTPUT FORMATTERINTERRUPTCONTROLLER(INT1, INT2)*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_ Figure 1.

2 UG-180 ADV7611 Reference Manual Rev. D | Page 2 of 184 TABLE OF CONTENTS Scope .. 1 Disclaimer .. 1 Functional Block Diagram .. 1 Revision History .. 5 Using the ADV7611 Hardware User Guide .. 6 Number Notations .. 6 Register Access Conventions .. 6 Acronyms and Abbreviations .. 6 Field Function Descriptions .. 8 Example Field Function Description .. 8 References .. 8 Introduction to the ADV7611 .. 9 hdmi Receiver .. 9 Component Processor .. 9 Main Features of ADV7611 .. 9 hdmi Receiver .. 9 Component Video Processing .. 9 Video Output Formats .. 10 Additional Features .. 10 Pin Configuration and Function Descriptions .. 11 Global Control Registers .. 13 ADV7611 Revision Identification .. 13 Power-Down Controls .. 13 Primar y Power-Down Controls .. 13 Secondary Power-Down Controls .. 13 Power-Down Modes .. 14 Global Pin Control .. 15 Reset Pin .. 15 Reset Controls .. 15 Tristate Output Drivers .. 15 Tristate LLC Driver .. 16 Tristate Synchronization Output Drivers.

3 16 Tristate Audio Output 16 Drive Strength Selection .. 17 Output Synchronization Selection .. 17 Output Synchronization Signals Polarity .. 18 Digital Synthesizer Controls .. 19 Crystal Frequency Selection .. 19 Primary Mode and Video Standard .. 20 Primary Mode and Video Standard Controls .. 20 V_FREQ .. 22 hdmi Decimation Modes .. 22 Primary Mode and Video Standard Configuration for hdmi Free Run .. 23 Recommended Settings for hdmi Inputs .. 23 Pixel Port Configuration .. 25 Pixel Port Output Modes .. 25 Bus Rotation and Reordering Controls .. 25 Pixel Data and Synchronization Signals Control .. 25 LLC 26 DLL on LLC Clock Path .. 26 Adjusting DLL Phase in All Modes .. 26 DLL Settings for 656, 8-/10-/12-Bit Modes .. 27 hdmi Receiver .. 28 +5 V Cable Detect .. 28 Hot Plug Assert .. 29 E-EDID/Repeater Controller .. 31 E-EDID Data 31 Notes .. 32 E-EDID Support for Power-Down Modes .. 32 Transitioning of Power Modes .. 32 Structure of Internal E-EDID.

4 32 Notes .. 33 TMDS Equalization .. 33 Port Selection .. 33 TMDS Clock Activity Detection .. 33 Important .. 34 Clock and Data Termination Control .. 34 hdmi /DVI Status Bits .. 34 Video 3D Detection .. 34 TMDS 35 TMDS Measurement after TMDS PLL .. 35 Deep Color Mode Support .. 36 Notes .. 36 Video FIFO .. 36 Pixel Repetition .. 38 HDCP Support .. 39 HDCP Decryption Engine .. 39 Internal HDCP Key OTP ROM .. 40 HDCP Keys Access Flags .. 40 ADV7611 Reference Manual UG-180 Rev. D | Page 3 of 184 HDCP Ri Expired .. 41 hdmi Synchronization Parameters .. 42 Notes .. 42 Horizontal Filter and Measurements .. 42 Primary Port Horizontal Filter Measurements .. 42 Horizontal Filter Locking Mechanism .. 44 Vertical Filters and Measurements .. 44 Primary Port Vertical Filter Measurements .. 44 Vertical Filter Locking Mechanism .. 47 Low Frequency Formats .. 47 Audio Control and Configuration .. 47 Important .. 48 Audio DPLL .. 48 Locking Mechanism .. 48 ACR Parameters Loading Method.

5 48 Audio DPLL Coast Feature .. 48 Audio FIFO .. 49 Audio Packet Type Flags .. 50 Notes .. 51 Audio Output Interface .. 52 I2S/SPDIF Audio Interface and Output Controls .. 53 Notes .. 54 MCLKOUT Setting .. 56 Audio Channel Mode .. 56 Audio Muting .. 57 Delay Line Control .. 57 Audio Mute Configuration .. 57 Internal Mute Status .. 60 AV Mute Status .. 60 Audio Mute Signal .. 60 Audio Stream with Incorrect Parity Error .. 61 Audio Clock Regeneration Parameters .. 61 ACR Parameters Readbacks .. 61 Monitoring ACR Parameters .. 61 Channel Status .. 62 Validity Status Flag .. 62 General Control and Mode Information .. 63 Category Code .. 64 Source Number and Channel Number .. 64 Sampling and Frequency Accuracy .. 65 Wo r d L e n g t h .. 65 Channel Status Copyright Value Assertion .. 66 Monitoring Change of Audio Sampling Frequency .. 66 Packets and InfoFrames Registers .. 66 InfoFrames Registers .. 66 InfoFrame Collection Mode .. 67 InfoFrame Checksum Error Flags.

6 67 AVI InfoFrame Registers .. 68 Audio InfoFrame Registers .. 69 SPD InfoFrame Registers .. 70 MPEG Source InfoFrame Registers .. 71 Vendor Specific InfoFrame Registers .. 72 Packet Registers .. 73 ACP Packet Registers .. 73 ISRC Packet 74 Gamut Metadata Packets .. 76 Customizing Packet/InfoFrame Storage Registers .. 77 Repeater Support .. 78 Repeater Routines Performed by the EDID/Repeater Controller .. 78 Repeater Actions Required by External Controller .. 79 HDCP Registers Available in Repeater Map .. 80 Interface to DPP Section .. 85 Notes .. 86 Pass Through Mode .. 86 4:2:2 Pass Through .. 86 4:4:4 Pass Through .. 86 Color Space Information Sent to the DPP and CP Sections . 87 Status Registers .. 87 hdmi Section Reset Strategy .. 90 hdmi Packet Detection Flag 90 Data Preprocessor and Color Space Conversion and Color Controls .. 91 Color Space Conversion Matrix .. 91 CP CSC Selection .. 91 Selecting Auto or Manual CP CSC Conversion Mode .. 92 Auto Color Space Conversion Matrix.

7 92 hdmi Automatic CSC 94 Manual Color Space Conversion Matrix .. 96 CSC in Pass-Through Mode .. 100 Color Controls .. 100 Component Processor .. 102 Introduction to the Component Processor .. 102 UG-180 ADV7611 Reference Manual Rev. D | Page 4 of 184 Clamp Operation .. 102 CP Gain 104 Features of Manual Gain Control .. 104 Features of Automatic Gain Control .. 104 Manual Gain and Automatic Gain Control Selection .. 104 Manual Gain Control .. 105 Manual Gain Filter Mode .. 107 Other Gain Controls .. 107 CP Offset 108 Notes .. 108 AV Code Block .. 109 CP Data Path for hdmi Modes .. 111 Pregain Block .. 111 Sync Processed by CP Section .. 114 Sync Routing from hdmi Section .. 114 Standard Detection and Identification .. 114 Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism .. 117 CP Output Synchronization Signal Positioning .. 121 CP Synchronization Signals .. 123 HSync Timing Controls .. 123 VSync Timing Controls .. 125 DE Timing Controls.

8 127 FIELD Timing Controls .. 128 HCOUNT Timing Control .. 132 CP hdmi Controls .. 133 Free Run Mode .. 133 Free Run Mode Thresholds .. 133 Free Run Feature in hdmi Mode .. 135 Free Run Default Color Output .. 136 CP Status .. 137 CP_REG_FF .. 137 CP Core Bypassing .. 137 Consumer Electronics Control .. 138 Main Controls .. 138 CEC Transmit Section .. 139 CEC Receive Section .. 141 Logical Address Configuration .. 141 Receive Buffers .. 142 CEC Message Reception Overview .. 145 Antiglitch Filter Module .. 146 Typical Operation Flow .. 147 Initializing CEC Module .. 147 Using CEC Module as Initiator .. 148 Using CEC Module as Follower .. 149 Low Power CEC Message Monitoring .. 150 Interrupts .. 152 Interrupt Architecture Overview .. 152 Interrupt Pins .. 155 Notes .. 155 Interrupt Duration .. 156 Interrupt Drive Level .. 156 Interrupt Manual Assertion .. 156 Multiple Interrupt Events .. 157 Description of Interrupt Bits .. 158 General Operation .. 158 hdmi Video Mode.

9 158 CEC .. 158 hdmi Only Mode .. 158 Additional Explanations .. 159 STDI_DATA_VALID_RAW .. 159 CP_LOCK, CP_UNLOCK .. 160 hdmi Interrupts Validity Checking Process .. 160 Storing Masked Interrupts .. 162 Register Access and Serial Ports Description .. 173 Main I2C Port .. 173 Register Access .. 173 IO I2C Map Address .. 173 Addresses of Other Maps .. 174 Protocol for Main I2C Port .. 175 DDC Ports .. 176 I2C Protocols for Access to the Internal EDID .. 176 I2C Protocols for Access to HDCP Registers .. 176 DDC Port A .. 176 Appendix A .. 177 PCB Layout Recommendations .. 177 Power Supply Bypassing .. 177 Example of a Current 177 Digital Outputs (Data and Clocks) .. 177 Digital Inputs .. 178 XTAL and Load Cap Value Selection .. 178 Example .. 178 ADV7611 Reference Manual UG-180 Rev. D | Page 5 of 184 Appendix B .. 179 Recommended Unused Pin Configurations .. 179 Appendix C .. 181 Pixel Output Formats .. 181 REVISION HISTORY 5/2017 Rev. C to Rev. D Changes to Audio Muting Section.

10 57 2/ 2014 Rev. B to Rev. C Changes to DDC_PWRDN, Addr 68 ( hdmi ), Address 0x73[0] Section .. 15 Changes to Code 0110; Table 21 Changes to HDMI_PORT_SELECT[2:0], Addr 68 ( hdmi ), Address 0x00[2:0] Section .. 33 Changes to Video 3D Detection Section .. 34 11/2012 Rev. A to Rev. B Deleted TDM from Table 3 .. 7 Deleted TDM Information from Introduction to the ADV7611 Section .. 9 Changes to Pin 1 and Pin 48 Descriptions .. 11 Changes to ADV7611 Revision Identification Section .. 13 Changes to Ta b l e 5 .. 14 Changes to INV_F_POL, IO, Address 0x06[3] Section .. 18 Changes to DLL Settings for 656, 8-/10-/12-Bit Modes Section and Added Table 9 .. 27 Changes to E-EDID Data Configuration Section .. 31 Changes to Figure 33 Changes to hdmi /DVI Status Bits Section .. 34 Added Low Frequency Formats Section and Figure 12 and Changes to Audio Control and Configuration Section .. 47 Changes to Table 12 .. 52 Deleted I2S_TDM_MODE_ENABLE, Addr 68 ( hdmi ), Address 0x6D[7] Section.