ATPL230A - Microchip Technology

1 Atmel-43053J- ATPL230A -Datasheet_22-Sep-1 6 DescriptionATPL230A is a power line communications base band modem, compliant with thePHY layer of PRIME ( power Line Intelligent Metering Evolution) is an open standard Technology used for Smart Grid applications like SmartMetering, Industrial Lighting and Automation, Home Automation, Street Lighting,Solar Energy and PHEV Charging Stations. ATPL230A PRIME device includes enhanced features such as additional robustmodes and frequency band extension. ATPL230A is able to operate in indepen-dently selectable transmission bands up to 472 kHz, achieving baud rates rangingfrom kbps up to kbps.

2 ATPL230A has been conceived to be bundled with an external Atmel MCU orMPU. Atmel provides a PRIME PHY layer library which is used by the externalMCU/MPU to take control of ATPL230A PHY layer Series power Line Communications DeviceDATASHEETATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 Modem power Line Carrier Modem for 50 Hz and 60 Hz mains 97-carriers OFDM PRIME compliant DBPSK, DQPSK, D8 PSK modulation schemes available Additional enhanced modes available: DBPSK Robust and DQPSK Robust Eight selectable channels between 42kHz and 472kHz available.

3 Only one channel can be active at atime Baud rate Selectable: to kbps Four dedicated buffers for transmission/reception Up to dB Vrms injected signal against PRIME load Up to dB of dynamic range in PRIME networks Automatic Gain Control and continuous amplitude tracking in signal reception Class D switching power amplifier control Integrated LDO regulator to supply analog functions Medium Access Control co-processor features Viterbi soft decoding and PRIME CRC calculation 128-bit AES encryption Channel sensing and collision pre-detection41,99288,86796, ,242206,055252,930260,742307.

4 617315,430362,305370,117416,992424,80547 1,680 CENELEC A - BCDARIBFCCCHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNEL 8f (kHz) 3 ATPL230A [DATASHEET] DiagramFigure 2-1. ATPL230A Functional Block DiagramADCVIMAVRPVRMVRCVIPAEMIT(0:5)TXRX 0 EMIT(6:11)TXRX1 EMITER_CTRLAGC_CTRLAGC(0:5)ZERO CROSS DETECTORVZ CROSSBERCDRSSIPHYCONTROLCLOCK & RESET INTERFACEARSTPLL INITCLKEACLKEBSRSTPOWER MANAGEMENTVDDPLL GNDVDDIN VDDOUT VDDIOVDDOUT ANCLKOUTT ransmission ChainVDDIN ANATPL230 APHY_COREBUF_RX1 TXDRV0 Recep on ChainAGNDSPI BRIDGE MOSIEINTMISOSCKCSTXDRV1 BUF_RX0 BUF_RX2 BUF_TX1 BUF_TX2 BUF_TX3 CINREVMCRCAESBUF_RX3 BUF_TX0 ATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 DescriptionTable Description ListSignal NameFunctionTypeActive LevelVoltage referenceCommentsPower digital supply.

5 Digital power supply mustbe decoupled by external to Digital LDO input to Analog LDO input to Analog LDO output. A capacitor in therange F - 10 F must be connected toeach Digital LDO output. A capacitor in therange F - 10 F must be connected toeach PLL supply. It must be decoupled by a100nF external capacitor, and connected toVDDOUT through a filter (Cut off frequency:25kHz) (1)Digital GroundPowerAGND(1)Analog GroundPowerClocks, Oscillators and PLLsCLKEA(2)External Clock Oscillator CLKEA must be connected to one terminalof a crystal (when a crystal is being used) orused as input for external clock signalInputVDDIOCLKEB(2)External Clock Oscillator CLKEB must be connected to one terminalof a crystal (when a crystal is being used)

6 Ormust be floating when an external clocksignal is connected through CLKEAI/OVDDIOCLKOUT10 MHz External Clock OutputOutputVDDIOR eset/TestARSTA synchronous ResetInputLowVDDIOI nternal pull up(3) SRSTS ynchronous ResetInputLowVDDIOI nternal pull up(3) PLL INITPLL Initialization SignalInputLowVDDIOI nternal pull up(3) PPLC (PRIME power Line Communications) TransceiverEMIT [0:11](4)PLC Tri-state Transmission portsOutputVDDIOAGC [0:5]Automatic Gain Control: These digital tri-state outputs are managedby AGC hardware logic to drive externalcircuitry when input signal attenuation isneededOutputVDDIO 5 ATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 Notes: 1.

7 Separate pins are provided for GND and AGND grounds. Layout considerations should be taken into account toreduce interference. Ground pins should be connected as shortly as possible to the system ground plane. Formore details about EMC Considerations, please refer to AVR040 application The crystal should be located as close as possible to CLKEA and CLKEB pins. See Table 10-7 on page See Table 10-5 on page Different configurations allowed depending on external topology and net Depending on whether an isolated or a non-isolated power supply is being used, isolation of this pin should betaken into account in the circuitry design.

8 Please refer to the Reference Design for further Front-End Transmission/Reception forTXDRV0 This digital output is used to modifyexternal coupling behavior inTransmission/Reception. The suitablevalue depends on the external circuitryconfiguration. The polarity of this pin can beinverted by Front-End Transmission/Reception forTXDRV1 This digital output is used to modifyexternal coupling behavior inTransmission/Reception. The suitablevalue depends on the external circuitryconfiguration.

9 The polarity of this pin can beinverted by CROSS(5)Mains Zero-Cross Detection Signal: This input detects the zero-crossing of themains voltageInputVDDIOI nternal pull down(3)VIMAN egative Differential Voltage InputInputVDDOUT ANVIPAP ositive Differential Voltage InputInputVDDOUT ANVRPI nternal Reference Plus Voltage. Connect anexternal decoupling capacitor between VRPand VRM (1nF - 100nF)OutputVDDOUT ANVRMI nternal Reference Minus Voltage. Connectan external decoupling capacitor betweenVRP and VRM (1nF - 100nF)OutputVDDOUT ANVRCC ommon-mode Voltage.

10 Bypass to analogground with an external decoupling capacitor(100pF - 1nF) OutputVDDOUT ANSerial Peripheral Interface - SPI CSSPI CS SPI bridge Slave SelectInputLowVDDIOI nternal pull up(3) SCKSPI SCK SPI bridge Clock signalInputVDDIOI nternal pull up(3) MOSISPI MOSI SPI bridge Master Out Slave InInputVDDIOI nternal pull up(3) MISOSPI MISO SPI bridge Master In Slave OutOutputVDDIOEINTPHY Layer External InterruptOutputLowVDDIOT able Description ListSignal NameFunctionTypeActive LevelVoltage referenceCommentsATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 and LQFP Package OutlineFigure 4-1.