Data Sheet ADIN1100 - Analog Devices

1 Data SheetADIN1100 Robust, Industrial, Low Power 10 BASE-T1L PHYRev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORTI nformation furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by AnalogDevices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject tochange without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices . Trademarks andregistered trademarks are the property of their respective 10 BASE-T1L IEEE Standard compliant Supports V p-p and V p-p transmit levels Supports intrinsic safety applications Cable reach <1700 meters with V p-p <1700 meters with V p-p Low power consumption Single supply 1 V p-p: 45 mW typical Dual supply 1 V p-p: 39 mW typical Diagnostics Frame generator and checker Multiple loopback modes IEEE test mode support Link and cable diagnostics MII, RMII, and RGMII MAC interfaces MDIO management interface Unmanaged configuration using pin strapping 25 MHz crystal or external clock input (50 MHz for RMII) Single or dual supply with V or V operation V, V, or V MAC interface VDDIO supply Integrated power supply monitoring and POR EMC test standards IEC 61000-4-4 EFT ( 4 kV) IEC 61000-4-2 ESD ( 4 kV contact discharge) IEC 61000-4-2 ESD ( 8 kV air discharge) IEC 61000-4-5 surge ( 4 kV) IEC 61000-4-6 conducted immunity (10 V/m) IEC 61000-4-3 radiated immunity (Class A) EN 55032 radiated emissions (Class B) Small package: 40-lead, 6 mm 6 mm LFCSP Temperature range Industrial: 40 C to +85 C Extended.

2 40 C to +105 CAPPLICATIONS Process control Factory automation Building automation Field instruments and switchesFUNCTIONAL BLOCK DIAGRAMF igure DESCRIPTIONThe ADIN1100 is a low power, single port, 10 BASE-T1L transceiverdesigned for industrial Ethernet applications and is compliant withthe IEEE Ethernet standard for long reach 10 Mbps single pair Ethernet (SPE). The ADIN1100 integrates anEthernet PHY core with all the associated Analog circuitry, input andoutput clock buffering, the management interface control registerand subsystem registers, as well as the MAC interface and controllogic to manage the reset, clock control, and pin ADIN1100 supports cable reach of up to 1700 meters withautonegotiation enabled and has ultra low power consumption of PHY core supports the V p-p operating mode and the Vp-p operating mode defined in the IEEE standard and canoperate from a single power supply rail of V or V, with thelower voltage option supporting the V p-p transmit voltage ADIN1100 has an integrated voltage supply monitoring circuitand power-on reset (POR)

3 Circuitry to improve system level MDIO interface is a 2-wire serial interface for communicationbetween a host processor or MAC and the ADIN1100 , therebyallowing access to control and status information in the PHY coremanagement registers. This interface is compatible with both theIEEE Standard Clause 22 and Clause 45 management SheetADIN1100 TABLE OF 0 | 2 of 1 Functional Block 5 Timing Interface Timing ..8 Absolute Maximum 9 Electrostatic Discharge (ESD) Configuration and Function 10 Typical Performance of Supply 14 Transmit Amplitude 16 Management 19 Reset 20 Status 20 Link Status 22 Power-Down Configuration 23 Unmanaged 23 Managed Configuration Pin Up 10 BASE-T1L 26 Unmanaged PHY PHY Generator and 30 Frame Generator and Checker Link 33 System Level Power Circuit 33 Component Compatibility (EMC) andElectromagnetic Immunity (EMI).

4 35 Register Register Clause 22 Register 39 MII Control 39 MII Status Identifier 1 Identifier 2 Access Control Access Clause 45 Register 42 PMA/PMD Control 1 Status 1 MMD Devices in Package MMD Devices in Package Control 2 Status 2 Transmit Disable 47 PMA/PMD Extended Abilities PMA/PMD Extended PMA/PMD Control PMA Control PMA Status Test Mode Control PMA Link Status 50 MSE Value 50 PCS Control 1 Status 1 50 PCS MMD Devices in Package 1 51 PCS MMD Devices in Package 2 51 PCS Status 2 5110 BASE-T1L PCS Control PCS Status 51 Autonegotiation MMD Devices in Package MMD Devices in Package Autonegotiation Control 52 BASE-T1 Autonegotiation Status Autonegotiation AdvertisementRegister, Bits[15:0].. 53 BASE-T1 Autonegotiation AdvertisementRegister, Bits[31:16].. 53 BASE-T1 Autonegotiation AdvertisementRegister, Bits[47:32].

5 54 BASE-T1 Autonegotiation Link Partner BasePage Ability Register, Bits[15:0].. 54 BASE-T1 Autonegotiation Link Partner BasePage Ability Register, Bits[31:16].. 55 Data SheetADIN1100 TABLE OF 0 | 3 of 78 BASE-T1 Autonegotiation Link Partner BasePage Ability Register, Bits[47:32] .. 55 BASE-T1 Autonegotiation Next PageTransmit Register, Bits[15:0].. 56 BASE-T1 Autonegotiation Next PageTransmit Register, Bits[31:16].. 56 BASE-T1 Autonegotiation Next PageTransmit Register, Bits[47:32].. 56 BASE-T1 Autonegotiation Link Partner NextPage Ability Register, Bits[15:0].. 56 BASE-T1 Autonegotiation Link Partner NextPage Ability Register, Bits[31:16].. 57 BASE-T1 Autonegotiation Link Partner NextPage Ability Register, Bits[47:32] .. 5710 BASE-T1 Autonegotiation Autonegotiation Status Forced Mode Autonegotiation Status 58 PHY Instantaneous Status Specific 1 MMD Identifier Specific 1 MMD Identifier Specific 1 MMDs in Specific 1 MMD Status Interrupt Status 60 System Interrupt Mask Reset 61 Software Power-Down Control Subsystem Reset 61 PHY MAC Interface Reset Status Power Management Control Interface Configuration Diagnostics Clock Control Configuration Values Control Mux Configuration 1 Mux Configuration 2 On/Off Blink Time On/Off Blink Time Control 65 LED Polarity Specific MMD 2 Device IdentifierHigh Specific MMD 2 Device IdentifierLow 68 Vendor Specific 2 MMDs in Specific MMD 2 Status Subsystem Interrupt Status Subsystem Interrupt Mask Checker Enable Checker Interrupt Enable Checker Transmit Select 70 Receive Error Count 70 Frame

6 Checker Count High Checker Count Low Checker Length Error Count Checker Alignment Error Checker Symbol Error Count Checker Oversized Frame Checker Undersized Frame Checker Odd Nibble Frame Checker Odd Preamble PacketCount 72 Frame Checker False Carrier Count Generator Enable Generator Control/Restart Generator Continuous Mode Generator Interrupt Enable Generator Frame Length Generator Interframe Gap Generator Number of Frames Generator Number of Frames Generator Done Configuration Interface Loopbacks Start of Packet (SOP) GenerationControl 75 PCB Layout 77 Land Placement and 77 Crystal Placement and SheetADIN1100 TABLE OF 0 | 4 of 78 Outline 78 Ordering HISTORY9/2021 Revision 0: Initial VersionData 0 | 5 of 78 AVDD_H = AVDD_L = VDDIO = V; DVDD_1P1 from internal low dropout (LDO) regulator (DVDD_1P1 = DLDO_1P1); all specifications at 40 C to +105 C, unless otherwise 1.

7 General SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsDIGITAL INPUTS/OUTPUTSA pplies to MAC interface pins, MDC,MDIO, INT, LINK_ST/PHYAD_2, RESET,and LED_xVDDIO = VInput Low Voltage (VIL) High Voltage (VIH) Low Voltage (VOL) low current (IOL) (minimum) = 2 mAOutput High Voltage (VOH) high current (IOH) (minimum) = 2 mAVDDIO = (minimum) = 2 (minimum) = 2 mAVDDIO = VDDIOVIOL (minimum) = 2 VDDIOVIOH (minimum) = 2 mARESET Deglitch sLED/LINK STATUS OUTPUTO utput Drive Current8mAVDDIO = V6mAVDDIO = V4mAVDDIO = VCLOCKSE xternal Crystal (XTAL)Requirements for external crystal used onXTAL_I/CLK_IN pin and XTAL_O pinCrystal Frequency25 MHzCrystal Frequency Tolerance 30+30ppmCrystal Drive Level<200 WCrystal ESR60 XTAL_I, XTAL_O Input Capacitance(CIN,EQ) parallel differential inputcapacitance looking into XTAL_I/CLK_INand XTAL_O pinsCrystal Load Capacitance (CL)11018pFIncluding PCB trace capacitance andXTAL_I, XTAL_O CIN,EQStart-Up Time2msCrystal oscillator onlyClock Input (CLK_IN)Clock Input Frequency25 MHzRequirements for external clock appliedto XTAL_I/CLK_IN pin, media independentinterface (MII) mode50 MHzReduced media independent interface(RMII) modeClock Input Voltage p-pAC-coupled sine or square wave at XTAL_I/CLK_IN pinClock Input Duty Cycle4555%XTAL_I Input Impedance (ZIN,EQ)Driving Point Resistance (RP)26k RP||CPDriving Point Capacitance (CP)23pFData 0 | 6 of 78 Table 1.

8 General SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsJitter Tolerance (RMS)40psCLK25_REF Clock OutputCLK25_REF = 10 pFVOL0 VLoad = 10 pFCLK25_REF Duty Cycle4555%Load = 10 pFLongTerm Jitter (RMS)40ps1 Load capacitance (CL) = ((C1 C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package and CP are the values of the equivalent parallel RC circuit to ac ground (RP||CP), modeling the driving point impedance of the XTAL_I/CLK_IN 2. 10 BASE-T1L SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsPOWER REQUIREMENTSS upply Voltage V p-p or V p-p transmit or , V p-p transmit , , or V p-p Transmit Level (Single Supply)AVDD_H = AVDD_L = VDDIO = V,DVDD_1P1 = DLDO_1P1 AVDD_x Supply Current, IAVDD25mAPower Consumption45mW100% data throughput, full activity11mWSoftware power-down V p-p Transmit Level (Dual Supply)AVDD_H = AVDD_L = VDDIO = V,DVDD_1P1 = external VAVDD_x Supply Current, IAVDD16mADVDD_1P1 Supply Current, IDVDD9mAPower Consumption39mW100% data throughput, full V p-p Transmit Level (Single Supply)AVDD_H = AVDD_L = VDDIO = V,DVDD_1P1 = DLDO_1P1 Supply Current, IAVDD33mAPower Consumption109mW100% data throughput, full activity22mWSoftware power-down V p-p Transmit Level (Dual Supply)

9 AVDD_H = V, AVDD_L = VDDIO = V,DVDD_1P1 = DLDO_1P1 AVDD_x Supply Current, Supply Current, IVDDIO15mAPower Consumption81mW100% data throughput, full activity11mWSoftware power-down V p-p Transmit Level (Triple Supply)AVDD_H = V, AVDD_L = VDDIO = V,DVDD_1P1 = external VAVDD_x Supply Current, Supply Current, IVDDIO6mADVDD_1P1 Supply Current, IDVDD9mAPower Consumption75mW100% data throughput, full activityTIMING/LATENCYMII LatencyData 0 | 7 of 78 Table 2. 10 BASE-T1L SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsTransmit (TX) Latency< s18-bit framesReceiver (RX) Latency< s32-bit framesTotal Latency 5 sData SheetADIN1100 TIMING 0 | 8 of 78 POWER-UP TIMINGT able supply ramp time40mst1 Minimum time interval to internal power good12043mst2 Hardware configuration latch time6814 st3 Management interface active50ms1 The minimum time interval is referenced to the last supply to reach its rising threshold.

10 There is no specific power supply sequencing 2. Power-Up TimingMANAGEMENT INTERFACE TIMINGT able period400nst2 MDC high time100nst3 MDC low time100nst4 MDC rise or fall time5nst5 MDIO signal setup time to MDC10nst6 MDIO signal hold time to MDC10nst7 MDIO delay time to MDC300nsFigure 3. Management Interface TimingData SheetADIN1100 ABSOLUTE MAXIMUM 0 | 9 of 78TA = 25 C, unless otherwise to GND V to +4 VDVDD_1P1, DLDO_1P1 to GND V to + VAVDD_H, AVDD_L to GND V to +4 VMAC Interface1, MDIO, MDC, INT to GND V to VDDIO + VTXN, TXP, RXN, RXP to GND V to AVDD + VLED_x, RESET, LINK_ST/PHYAD_2 to GND V to VDDIO + VXTAL_I/CLK_IN to GND V to + VXTAL_O, CLK25_REF to GND V to + VOperating Temperature Range (TA)Industrial 40 C to +105 CStorage Temperature Range 65 C to +150 CJunction Temperature (TJ max)125 CPower Dissipation(TJ max TA)/ JALead TemperatureJEDEC industry standardSolderingJ-STD-0201 See the Pin Configuration and Function Descriptions section for the full list ofMAC interface at or above those listed under Absolute Maximum Ratingsmay cause permanent damage to the product.