Data Sheet ADIN1110 GENERAL DESCRIPTION - Analog …

1 Data SheetADIN1110 Robust, Industrial, Low Power 10 BASE-T1L Ethernet MAC-PHYRev. BDOCUMENT FEEDBACK TECHNICAL SUPPORTI nformation furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by AnalogDevices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject tochange without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective 10 BASE-T1L IEEE Standard compliant Cable reach up to 1700 m with V Integrated MAC with SPI Supports OPEN Alliance 10 BASE-T1x MAC-PHY serialinterface 16 MAC address filters High and low priority queues with 28 kB buffer Cut through or store forward operation IEEE 1588 timestamp support Statistics counters Low power consumption.

2 42 mW (dual-supply, V p-p) Diagnostics Cable fault detection with TDR Link quality indicator with MSE Frame generator and checker Multiple loopback modes IEEE test mode support Supports V p-p and V p-p transmit levels 4-pin MDI (RXN, RXP, TXN, and TXP) Suitable for intrinsic safety applications External termination resistors Autonegotiation 25 MHz crystal or external clock input Electromagnetic compatibility (EMC) test standards IEC 61000-4-4 electrical fast transient ( 4 kV) IEC 61000-4-2 ESD ( 4 kV contact discharge) IEC 61000-4-2 ESD ( 8 kV air discharge) IEC 61000-4-6 conducted immunity (10 V/m) IEC 61000-4-5 surge ( 4 kV) IEC 61000-4-3 radiated immunity (Class A) EN55032 radiated emissions (Class B) Small package: 40-lead (6 mm 6 mm) LFCSP Temperature range Industrial: 40 C to +85 C Extended: 40 C to +105 CAPPLICATIONS Field instruments Building automation and fire safety Factory automation Edge sensors and actuators Condition monitoring and machine connectivityFUNCTIONAL BLOCK DIAGRAMF igure DESCRIPTIONThe ADIN1110 is an ultra low power, single port, 10 BASE-T1 Ltransceiver design for industrial Ethernet applications and is com-pliant with the IEEE Ethernet standard for longreach, 10 Mbps single pair Ethernet (SPE).

3 Featuring an integratedmedia access control (MAC) interface, the ADIN1110 enables directconnectivity with a variety of host controllers via a 4-wire serialperipheral interface (SPI). This SPI enables the use of lower powerprocessors without an integrated MAC, which provides for thelowest overall system level power consumption. The SPI can beconfigured to use the Open Alliance SPI protocol or a generic programmable transmit levels, external termination resistors,and independent receive and transmit pins make the ADIN1110suited to intrinsic safety ADIN1110 has an integrated voltage supply monitoring andpower-on reset (POR) circuitry to improve system level ADIN1110 is available in a 40-lead, 6 mm 6 mm lead framechip scale package (LFCSP).

4 Analog Devices is in the process of updating documentation toprovide terminology and language that is culturally appropriate. Thisis a process with a wide scope and will be phased in as quickly aspossible. Thank you for your SheetADIN1110 TABLE OF B | 2 of 1 Functional Block 4 Timing Maximum 8 Electrostatic Discharge (ESD) Configuration and Function 9 Typical Performance 11 Theory of Supply Front 12 MAC .. 12 Transmit Amplitude Status 16 Power-Down Configuration 17 Managed Configuration Pin Up 10 BASE-T1L 19 Unmanaged PHY PHY Generator and 23 Test Domain Reflectometry (TDR).

5 24 Applications 26 System Level Power Circuit 26 Component Compatibility (EMC) andElectromagnetic Immunity (EMI).. 29 MAC 45 SPI Register Clause 22 Register 68 PHY Clause 45 Register 71 PCB Layout 106 Package Placement and 106 Crystal Placement and 107 Ordering HISTORY9/2023 Rev. A to Rev. BChanges to GENERAL DESCRIPTION to Evaluation 1072/2023 Rev. 0 to Rev. AChange to Features to Applications to GENERAL DESCRIPTION Table 1, Renumbered Table 1; Renumbered to Table 2 5 Changes to Table 8 ..9 Change to Figure 11 Added Analog Front-End 12 Changes to Interrupt (INT) Transmit Amplitude Configuration 12 Data SheetADIN1110 TABLE OF B | 3 of 107 Added Master/Slave Configuration Software Configuration Section and Table 13 Changed MDI Interface Section to MDI to Table to Hardware Configuration Pins Unmanaged Applications Managed Applications Table Time Domain Reflectometry (TDR)

6 24 Added Fault Detection with the TDR Engine 24 Added TDR Offset Calibration 24 Added Cable Calibration Length/Distance to Fault Accuracy Section and Table to Component Recommendations Crystal Section to External Crystal Oscillator to External Crystal Oscillator Section and Figure External Clock Input Section to External 25 MHz Clock Input to External 25 MHz Clock Input Section and Figure Table to MAC SPI Section ..30 Added SPI to Transmit Data Header Section and Table to Receive Data Footer to OPEN Alliance SPI Cut Through Mode to Control Transactions Section and Table SPI Register Map Section to SPI Register Details MAC to Frame Filtering on Receive PHY Clause 45 Register Map Section to PHY Clause 45 Register Details 71 Change to Component Placement and Routing 10610/2021 Revision 0: Initial VersionData B | 4 of 107 AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 supplied from internal low dropout (LDO) regulator (DVDD_1P1 = DLDO_1P1), and allspecifications are at 40 C to +105 C, unless otherwise 1.

7 GENERAL SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsDIGITAL INPUTS/OUTPUTSA pplies to SPI pins, SWPD_EN, TX2P4_EN, TS_TIMER/MS_SEL, TS_CAPT, INT, LINK_ST, RESET, and LED_xVDDIO = VInput Low Voltage (VIL) High Voltage (VIH) Low Voltage (VOL) low current (IOL) (minimum) = 2 mAOutput High Voltage (VOH) high current (IOH) (minimum) = 2 mAVDDIO = (minimum) = 2 (minimum) = 2 mAVDDIO = VDDIOVIOL (minimum) = 2 VDDIOVIOH (minimum) = 2 mARESET Deglitch sLED OUTPUTO utput Drive Current8mAVDDIO = V6mAVDDIO = V4mAVDDIO = VCLOCKSE xternal Crystal (XTAL)Requirements for external crystal used on XTAL_I pin andXTAL_O pinCrystal Frequency25 MHzCrystal Frequency Tolerance 30+30ppmCrystal Drive Level<200 WCrystal Equivalent Series Resistance (ESR)60 XTAL_I, XTAL_O Input Capacitance (CIN,EQ) parallel differential input capacitance lookinginto XTAL pinsCrystal Load Capacitance (CL)11018pFIncluding printed circuit board (PCB) trace capacitanceand XTAL_I, XTAL_O CIN,EQStart-up Time2msCrystal oscillator onlyClock Input (CLK_IN)

8 Clock Input Frequency25 MHzRequirements for external clock applied to XTAL_I pinClock Jitter40psRMSC lock Input Voltage p-pSine or square wave at XTAL_I/CLK_IN pin, see External25 MHz Clock Input section for more informationClock Input Duty Cycle4555%XTAL_I Input Impedance (ZIN,EQ)Driving Point Resistance RP26k Rp||CpDriving Point Capacitance CP23pFCLK25_REF Clock OutputCLK25_REF Frequency25 MHzData B | 5 of 107 Table 1. GENERAL Specifications (Continued)ParameterMinTypMaxUnitTest 10 pFVOL0 VLoad 10 pFCLK25_REF Duty Cycle4555%Load 10 pFCLK25_REF Frequency Tolerance 50+50ppm1CL = ((C1 C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package and Cp are the values of the equivalent parallel RC circuit to ac ground (Rp||Rc), modeling the driving point impedance of the XTAL_I/CLK_IN 2.

9 10 BASE-T1L SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsPOWER REQUIREMENTSS upply Voltage V p-p or V p-p transmit or , V p-p transmit , , V p-p Transmit Level (Single Supply)AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 =DLDO_1P1 AVDD_x Supply Current, IAVDD28mAPower Consumption50mW100% data throughput, full V p-p Transmit Level (Dual Supply)AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 =external VAVDD_x Supply Current, IAVDD16mADVDD_1P1 Supply Current, IDVDD12mAPower Consumption42mW100% data throughput, full V p-p Transmit Level (Single Supply)AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 =DLDO_1P1 AVDD_x Supply Current, IAVDD36mAPower Consumption119mW100% data throughput, full V p-p Transmit Level (Dual Supply)AVDD_H = V, AVDD_L = VDDIO = V, DVDD_1P1= DLDO_1P1 AVDD_x Supply Current, Supply Current, IVDDIO18mAPower Consumption87mW100% data throughput, full V p-p Transmit Level (Triple Supply)

10 AVDD_H = V, AVDD_L = VDDIO = V, DVDD_1P1= external VAVDD_x Supply Current, Supply Current, IVDDIO6mADVDD_1P1 Supply Current, IDVDD12mAPower Consumption78mW100% data throughput, full activityANALOG INPUTS AND OUTPUTSMDI Gain Offset + SheetADIN1110 TIMING B | 6 of 107 POWER-UP TIMINGT able 3. Power-Up TimingParameterDescriptionMinTypMaxUnitt RAMPP ower supply ramp time40mst1 Minimum time interval to internal power good12043mst2 Hardware configuration latch time6814 st3 Management interface (SPI) active50ms1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing 2.