Datasheet - S2-LP - Ultra-low power, high performance, sub ...

1 Features Frequency bands: 413-479 MHz (S2-LPQTR) 452-527 MHz (S2-LPCBQTR) 826-958 MHz (S2-LPQTR) 904-1055 MHz (S2-LPCBQTR) Modulation schemes: 2(G)FSK, 4(G)FSK OOK, ASK Air data rate from to 500 kbps Ultra-low power consumption: 7 mA RX 10 mA TX @ +10 dBm Excellent performance of receiver sensitivity: down to -130 dBm Excellent receiver selectivity and blocking Programmable RF output power up to +16 dBm Programmable RX digital filter Programmable channel spacing Fast start-up and frequency synthesizer settling time Automatic frequency offset compensation, AGC and symbol timing recovery More than 145 dB RF link budget Battery indicator and low battery detector RX and TX 128 bytes FIFO buffers 4-wire SPI interface Automatic packet acknowledgment and retransmission Embedded timeout protocol engine Excellent receiver selectivity (> 80 dB @ 2 MHz)

2 ST companion integrated balun/filter chips are available Antenna diversity algorithm Fully integrated Ultra-low power RC oscillator Wake-up driven by internal timer or external event Digital real time RSSI Flexible packet length with dynamic payload length Programmable preamble and SYNC word quality filtering and detection Embedded CSMA/CA engine based on listen-before-talk systems IEEE hardware packet support with whitening, FEC, CRC and dualSYNC word detection Wireless M-BUS supported KNX-RF supported Enables operations in the SIGFOX and MONARCH networksMaturity status linkS2-LPUltra-low power, high performance, sub-1 GHz transceiverS2-LPDatasheetDS11896 - Rev 7 - September 2020 For further information contact your local STMicroelectronics sales Suitable to build systems targeting: Europe: ETSI EN 300 220, category natively compliant, ETSI EN 303131 US: FCC part 15 and part 90 Japan: ARIB STD T67, T108 China: SRRC Operating temperature range: -40 C to +105 CApplications Sensors to Cloud Smart metering Home energy management systems Wireless alarm systems Smart home Building automation Industrial monitoring and control Smart lighting systemsS2-LPDS11896 - Rev 7page 2/901 DescriptionThe S2-LP is a high performance Ultra-low power RF transceiver , intended for RF wireless applications in thesub-1 GHz band.

3 It is designed to operate in both the license-free ISM and SRD frequency bands at 433, 512,868 and 920 MHz, but can also be programmed to operate at other additional frequencies in the 413-479 MHz,452-527 MHz, 826-958 MHz, 904-1055 MHz S2-LP supports different modulation schemes: 2(G)FSK, 4(G)FSK, OOK and ASK. The air data rate isprogrammable from to 500 S2-LP can be used in systems with channel spacing down to 1 kHz enabling the narrow band S2-LP shows an RF link budget higher than 140 dB for long communication ranges and meets the regulatoryrequirements applicable in territories worldwide, including Europe, Japan, China and the - Rev 7page 3/902 Detailed functional descriptionThe S2-LP integrates a configurable baseband modem with proprietary fully programmable packet formatallowing also: IEEE applications The hardware packet supports whitening, CRC, FEC and dual SYNC word detection.

4 Wireless M-Bus applicationsIn order to reduce the overall system power consumption and increase the communication reliability, the S2-LPprovides an embedded programmable automatic packet acknowledgment, automatic packet retransmission,CSMA/CA engine, low duty cycle protocol, RX sniff mode and timeout S2-LP fully supports antenna diversity with an integrated antenna switching control data bytes are buffered in two different 128 bytes FIFOs (TX FIFO and RX FIFO),accessible via SPI interface for host addition, the reduced number of external components enables a cost effective solution permitting a compactPCB S2-LP targets volume applications like: Sensors to Cloud Smart metering Home energy management systems Wireless alarm systems Smart home Building automation Industrial monitoring and controlFigure 1.

5 Simplified S2-LP block diagramS2-LPDetailed functional descriptionDS11896 - Rev 7page 4/90 The receiver architecture is low-IF conversion, the received RF signal is amplified by a two-stage low-noiseamplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). LNA and IFamplifiers make up the RX front-end (RXFE) and have programmable gain. At IF, the ADCs digitalize the I/Qsignals. The demodulated data go to an external MCU either through the 128-byte RX FIFO, readable via SPI, ordirectly using a programmable GPIO transmitter part of the S2-LP is based on direct synthesis of the RF frequency. The power amplifier (PA) inputis the LO generated by the RF synthesizer, while the output level can be configured between -30 dBm and +14dBm (+16 dBm in boost mode), at antenna level with dB data to be transmitted can be provided by an external MCU either through the 128-byte TX FIFO writable viaSPI, or directly using a programmable GPIO pin.

6 The S2-LP supports frequency hopping, TX/RX and antennadiversity switch control, extending the link range and improving S2-LP has a very efficient power management (PM) system. An integrated switched mode power supply(SMPS) regulator allows operation from a battery voltage ranging from + V to + V, and with powerconversion efficiency of 90%.A crystal must be connected between XIN and XOUT. It is digitally configurable to operate with different an alternative, an external clock signal can be used to feed XIN for proper operation. The S2-LP also has anintegrated low-power RC oscillator, generating the kHz signal used as a clock for the slowest standard 4-pin SPI bus is used to communicate with the external MCU. Four configurable general purpose I/Osare functional descriptionDS11896 - Rev 7page 5/903 Typical application diagram and pin descriptionThis section describes three different application diagrams for the S2-LP .

7 Two main configurations are available: HPM (high performance mode) configuration LPM (low power mode) configurationIn the LPM operating mode the LDOs are bypassed and the SMPS provides the regulator voltage at V. Notethat in LPM the PA is supplied from SMPS at V (instead of V as in HPM), so the max. output power islower than HPM. The figure below shows the suggested configuration with discrete matching network and 2. Suggested application diagram (embedded SMPS used)C29C21L8C6L7C14L6S2-LPVDDSMPS1 SMPS12 SMPS23 XOUT4 XIN5 SDN6 VDDANASYNTH7 VRSYNTH8 VREFVCO9 VDDVCOTX10TX11 VRRF12 VRDIG24 GPIO323 GPIO222 GPIO121 GPIO020 CSN19 SCLK18 SDI17 SDO16 VDDRXDIG15 RXP14 RXN13 GND25C0C13C2C32L5C5C30C10L9 XTALL0C11C3L3C16L10C28C17C4C1C31 SHUTDOWNVBATTVSMPS2 VBATTVBATTVSMPS2 VBATTD igital interfaceFigure 3.

8 Suggested application diagram (embedded SMPS not used) shows the suggested configuration withdiscrete matching network and SMPS-OFF application diagram and pin descriptionDS11896 - Rev 7page 6/90 Figure 3. Suggested application diagram (embedded SMPS not used)C28 XTALC16C11L8C0C30U3S2-LPVDDSMPS1 SMPS12 SMPS23 XOUT4 XIN5 SDN6 VDDANASYNTH7 VRSYNTH8 VREFVCO9 VDDVCOTX10TX11 VRRF12 VRDIG24 GPIO323 GPIO222 GPIO121 GPIO020 CSN19 SCLK18 SDI17 SDO16 VDDRXDIG15 RXP14 RXN13 GND25L5L6C10C13L10C29C14C6C31C21L9L3C32L 7C17C3C5C2C4 SHUTDOWNEXT = VSMPS2 VBATTVBATTVBATTVSMPS2 VBATTD igital interfaceFigure 4. Suggested application diagram HPM/LPM (integrated balun, embedded SMPS used)C2L0C0C3C4C16C6C5C21 BALF-SPI2RX_PRX_NTXGNDGNDANTL7S2-LPVDDSM PS1 SMPS12 SMPS23 XOUT4 XIN5 SDN6 VDDANASYNTH7 VRSYNTH8 VREFVCO9 VDDVCOTX10TX11 VRRF12 VRDIG24 GPIO323 GPIO222 GPIO121 GPIO020 CSN19 SCLK18 SDI17 SDO16 VDDRXDIG15 RXP14 RXN13 GND25 XTALC1 SHUTDOWNVBATTVSMPS2 VBATTVBATTVSMPS2 VBATTD igital interfaceS2-LPTypical application diagram and pin descriptionDS11896 - Rev 7page 7/90 Table 1.

9 Description of the external components of the typical application diagramsComponentsHPM/LPM discrete balunHPM/LPMintegrated balunDescriptionSMPS ONSMPS OFFC0 XXXD ecoupling capacitor for on-chip voltage regulator todigital partC1X-XSMPS LC filter capacitorsC2, C3 XXXC rystal loading capacitorsC4 XXXD ecoupling capacitor for on-chip voltage regulator tosynthesizer (LF part)C5 XXXD ecoupling capacitor for band-gap voltage referenceof VCO regulatorC6 XXXD ecoupling capacitor for on-chip voltage regulator toLNA-MIXERC29, C30, C31, C32 XXTX LC filter/matching capacitorsC11, C13 XXDC blocking capacitorsC16, C21 XXXC10, C14, C17 XXRF balun/matching capacitorsL0X-XSMPS LC filter inductorL7 XXXRF choke inductor or resonating inductor (upon RFnetwork topology)L8, L9, L10 XXTX LC filter/matching inductorsL3, L5, L6 XXRX balun/matching inductorsXTALXXXC rystalS2-LPTypical application diagram and pin descriptionDS11896 - Rev 7page 8 diagramFigure 5.

10 Pin diagram, QFN24 (4x4 mm) packageS2-LPQTRVR DIGVDD SMPSSMPS1 SMPS2 XOUTXINSDNVR RFVREF VCOVDD ANA/SYNTHVR SYNTHVDD TX/VCOTXGPIO 3 GPIO 2 GPIO 1 GPIO 0 CSn1234567891011121314151617181920212223 24 SCLKSDISDOVDD DIG/RXRX+RX-25 - descriptionTable 2. PinoutNumberPin namePin typeDescription1 VDD V to V analog power supply for SMPS V to V SMPS regulator output to be externally filtered3 SMPS2 Analog V to V SMPS voltage input after LC filtering applied to SMPS1 output4 XOUTA nalog outCrystal oscillator output. Connect to an external crystal or leave floating if drivingthe XIN pin with an external clock source5 XINA nalog inCrystal oscillator input. Connect to an external crystal or to an external clocksource. If using an external clock source, DC coupling with a minimum VDClevel is recommended and minimum AC amplitude of 400 mVpp (however, theinstantaneous level at input cannot exceed the 0 V range)6 SDND igital inShutdown input pin.