EE559: MOS VLSI Design - College of Engineering

1 ee559 MOS vlsi DesignPrepared by CK & KR1EE559: MOS vlsi DesignIt t KRInstructors: K. RoyEmail: ~kaushikOffice: MSEE 232 Telephone: 494-2361 Office Hours:Tuesday/Thursday 11am-12noonbittor by appointmentsGrading Policy Mid-terms + quizzes + hw will account for 75% of the grade 3 mid-terms Mandatory and has to be taken on the scheduled day of the exam. Project will account for 25% of the grade. Late projects will not be accepted. You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above.

2 Any form of cheating will be heavily penalized and reported to the Dean of students and may result in a failing Instructor reserves right to change project requirements. ee559 MOS vlsi DesignPrepared by CK & KR2 Text and References Text:Text: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall, Second edition References: Principles of cmos vlsi Design : A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley Circuits, Interconnects, and Packaging for vlsi , H.

3 Bakoglu, Addison Wesley Class Notes: ~ vlsi / ee559 /20001 Conferences & Journals IEEE Transactions on vlsi Systems IEEE Transactions on CAD of IC sIEEE Transactions on CAD of IC s IEEE Journal of Solid State Circuits IEEE vlsi Circuits Symposium Journal of Electronic Testing ACM Design Automation Conference IEEE International Conference on CAD IEEE Solid State Circuits Conference International symposium on Low-Power Electronics & Design IEEE Conference on Computer Design IEEE International Test ConferenceEE559 MOS vlsi

4 DesignPrepared by CK & KR3 Course Outline Introduction: Historical perspective and Future Trend Semiconductor DevicesCMOS Logic Layout techniques cmos Logic, Layout techniques MOS devices, SPICE models Inverters: transfer characteristics, static and dynamic behavior, power and energy consumption of static MOS inverters Designing combinational logic gates in cmos Static cmos Design : Complementary cmos , ratioed logic, pass-transistor logic Dynamic cmos logicCourse Outline (Cont d) Designing combinational logic gates (Cont d)

5 Power consumption in cmos gatespg Low-power Design Designing sequential circuits Interconnect and timing issues Designing memory and array structures Designing arithmetic building blocksSf vlsi testing and verificationEE559 MOS vlsi DesignPrepared by CK & KR4 vlsi CAD Lab and TA vlsi CAD Lab located in 360 Potter Engineering Center SUN workstations running Mentor Graphics tools Courtesy key for after-hour access can be obtained from front desk in Potter Engineering Library Additional workstations in MSEE 186 Lab TA: Kuntal Roy Facilitates the use of lab Design tools.

6 Office hours: TBA Lab Orientation will be held in the second week Lab URL ~ Project Complete Design of a functional logic block or system Complexity of 1000+ transistors or novelty Design using the CADENCE tools and HSPICE Design your own library from scratch Functionality to be verified Critical path timing should be verified using HSPICE Project report due the last day of class Project presentation by each group in the last week of class Work in a group of 2 will be allowed in special cases Start early!

7 Start early! Emphasis on new ideas, power dissipation, performance, reconfigurability, low voltage designEE559 MOS vlsi DesignPrepared by CK & KR5 Introduction:A Historical Perspective and Future TrendsReferences: Adapted from: Digital Integrated Circuits: A Design Perspective, pgggp,J. Rabaey UCBP rinciples of cmos vlsi Design : A Systems Perspective, 2nd Ed., N. H. E. Weste and K. EshraghianDigital Computation: Particle Location is an Indicator of State110010EE559 MOS vlsi DesignPrepared by CK & KR6 Physical Medium for Computation: Barrier ModelV=0 SOURCEDRAINGATEEbV=Vmin=EbminToxLeffVgVd 1.

8 Can we operate with Vmin~ KBTln2 ?2. Can we operate with Qmin= q ? ee559 MOS vlsi DesignPrepared by CK & KR7 The First Computer The Babbage Differential gEngine (1834) 25,000 mechanical parts Cost 17,470 Digital Electronic Computing Started with the introduction of vacuum tube ENIAC for computing artillery firing tables in 1946 ENIAC for computing artillery firing tables in 1946 Integration density 80 feet long, feet high, and several feet wide 18,000 vacuum tubes Reliability issues and excessive power consumption Did not go far until the invention of the transistor at Bell Lab in 1947EE559 MOS vlsi DesignPrepared by CK & KR8 HISTORY MOS field-effect transistor.

9 Lilienfeld (1925), Heil (1935) Bipolar transistors: Bardeen (1947), Schockley (1949) First Bipolar digital logic: Harris (1956)First Bipolar digital logic: Harris (1956) IC Logic family: Transistor-Transistor Logic (TTL) (1962) Emitter-Coupled Logic (ECL) (1971) Integrated Injection Logic (I2L) (1972) PMOS and NMOS transistors on the same substrate: Weimer (1962), Wanlass (1965)(),() PMOS-only logic until 1971 when NMOS technology emerged NMOS-only logic until late 1970s, when cmos technology took over Later developments.

10 BiCMOS, GaAs, low-temperator cmos , super-conducting technologies, Nano-electronicExponential Increase in Leakage Non-SiliconSiliconSilicon1 m100 nm10 nm1970 1980 2000 2010 20205 mNonSilicon TechnologySilicon Micro- electronicsSilicon Nano- electronicsGateSSubthreshold LeakageGate Leakage% of Total)40%50%Must stop at 50%610 ONOFFII=310 ONOFFII=2~6~10 ONOFFIIJ unctionleakageSourcen+n+BulkDrainA. Grove, IEDM 2002 Technology ( )Leakage Power (%0%10%20%30% MOS vlsi DesignPrepared by CK & KR9 Technology TrendBuried Oxide (BOX)SubstrateFully-depleted bodyGateVGVSVDD rainSourceVbackBuried Oxide (BOX)SubstrateFully-depleted bodyGateVGVSVDD rainSourceVbackBulk-CMOSFD/SOINano devices Carbon nanotubeIII-V devices nano-wiresSpintronicsDGMOSFinFETT rigateBuried Oxide (BOX)SubstrateSourceFloating BodyDrainGateVSVGVDB uried Oxide (BOX)