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High-End Performance Packaging: 3D/2.5D Integration 2020

From Technologies to Markets 2020 High-End Performance Packaging: 3 Integration 2020 Market and Technology ReportSample2 Tableofcontents2 Scopeofreport4 Reportmethodologies&definitions6 Keyfeaturesofthisreport5 Abouttheauthor7 YoleGroupofcompaniesrelatedreports9 Glossaries11 Companiescitedinthisreport12 3-Pagesummary13 Executivesummary17 Context66oSemiconductorindustry playerspursuingMoore slaw67oHigh-endperformancepackagingdefin ition71oScopeofreport72oHigh-endperforma ncepackagingmarketsegment73oHigh-endperf ormancepackagingintroduction74 Marketforecasts75oMarketRevenue76oTotalm arketrevenueoSplitbyend-marketoSplitbyte chnologyoMarketUnits80oTotalmarketunitso Splitbyend-marketoSplitbytechnologyHigh- end Performance Packaging: 3 Integration 2020 | Sample | | 2020 TABLE OF CONTENTSPart 1 Markettrends96oCloud&edgecomputing97oClo udcomputingandnetworking103oHigh-Perform anceComputing(HPC)111oArtificialintellig enceforautonomousvehicles119oChapterconc lusion125 Commercializedproductsanditssupplychain1 27oProductlaunches130o3 Dstackedmemorieso(x)PUoGPUforHPCoSupplyc hainforhigh-endperformancepackaging156oG lobalmappingofhigh-endpackagingoGlobalma ppingbasedontechnologyoSupplychainforhig h-endpackagingproductsoLatestprogressofk eyplayers1753oSupplychainanalysisinhigh- endperformancepackaging188oPackaging supply chain analysisoAnalyst s point of view on supply

o Cloud computing and networking 103 o High-Performance Computing (HPC) 111 o Artificial intelligence for autonomous vehicles 119 o Chapter conclusion 125 Commercialized products and its supply chain 127 o Product launches 130 o 3D stacked memories o (x)PU o GPU for HPC o Supply chain for high-end performance packaging 156

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Transcription of High-End Performance Packaging: 3D/2.5D Integration 2020

1 From Technologies to Markets 2020 High-End Performance Packaging: 3 Integration 2020 Market and Technology ReportSample2 Tableofcontents2 Scopeofreport4 Reportmethodologies&definitions6 Keyfeaturesofthisreport5 Abouttheauthor7 YoleGroupofcompaniesrelatedreports9 Glossaries11 Companiescitedinthisreport12 3-Pagesummary13 Executivesummary17 Context66oSemiconductorindustry playerspursuingMoore slaw67oHigh-endperformancepackagingdefin ition71oScopeofreport72oHigh-endperforma ncepackagingmarketsegment73oHigh-endperf ormancepackagingintroduction74 Marketforecasts75oMarketRevenue76oTotalm arketrevenueoSplitbyend-marketoSplitbyte chnologyoMarketUnits80oTotalmarketunitso Splitbyend-marketoSplitbytechnologyHigh- end Performance Packaging: 3 Integration 2020 | Sample | | 2020 TABLE OF CONTENTSPart 1 Markettrends96oCloud&edgecomputing97oClo udcomputingandnetworking103oHigh-Perform anceComputing(HPC)111oArtificialintellig enceforautonomousvehicles119oChapterconc lusion125 Commercializedproductsanditssupplychain1 27oProductlaunches130o3 Dstackedmemorieso(x)PUoGPUforHPCoSupplyc hainforhigh-endperformancepackaging156oG lobalmappingofhigh-endpackagingoGlobalma ppingbasedontechnologyoSupplychainforhig h-endpackagingproductsoLatestprogressofk eyplayers1753oSupplychainanalysisinhigh- endperformancepackaging188oPackaging supply chain analysisoAnalyst s point of view on supply chain192oIt is a new battlefield for technology supremacyoImpact within big playersoImpact on OSATs & substrate suppliersoWhat is TSMC strategy exactly?

2 OWho are the winners/losers?oChapterConclusion201 IPAnalysis:3 DSoC hybridbonding203oPatentoverview204oSuppl ychainIPposition(examples)208oChaptercon clusion212 Technologytrends214oTechnologyroadmap215 oSemiconductorpackagingroadmapoAdvancedp ackagingroadmapoHigh-endpackagingroadmap :iOpitchvsIOdensityoHigh-endpackagingroa dmap:application-technologyoKeyplayer stechnologyroadmap221oShortdescriptionof chiplet227o3 DSoC230oHybridbonding234oKeyplayers technologies:hybridbondingfor3 DSoCHigh-end Performance Packaging: 3 Integration 2020 | Sample | | 2020 TABLE OF CONTENTSPart 2/2oTSVprocess254o3 Dstackedmemory260oHBMo3 DStacking(3DS)DRAMo3 DSRAMo3 DNANDoOthers:HMC, (UHDFO)295oEmbeddedSibridge301oOtherhigh -endpackagingtechnologies310oChapterconc lusion315 Reportconclusion318 Appendix320oOSAT shigh-endpackagingtechnologies321 Yolecorporatepresentation3304 The main objectives of this report are: To identify and describe which technologies can be classified as High-End Performance packaging To define High-End Performance packaging To analyze key market drivers, benefits and challenges of High-End Performance packaging by application To describe the different existing technologies, their trends and roadmaps To analyze the supply chain and High-End Performance packaging landscape To update the business status of High-End Performance packaging technology markets To provide a market forecast for the coming years, and estimate future trendsFan-out packaging markets are studied from the following angles: Top-down based on end-systems demand Market valuations based on top-down and bottom-up models Market shares based on production projections Supply value chain analysis State-of-the-art technologies and trends End-user application adoptionsHigh-end Performance Packaging.

3 3 Integration 2020 | Sample | | 2020 SCOPE OF THE REPORTAre your needs beyond this report s scope?Contact us for a custom:5 YoleD veloppement sdefinitionofhigh-endperformancepackagin g High-endperformancepackagingmarketsegmen tation Marketvaluationintermsofpackageunits,rev enueandwaferproductionvolumes Marketvaluationofkeyhigh-endpackagingtec hnologies IncludesCOVID-19impactinallforecasts High-endperformancepackagingmarkettrends :end-systemdrivers Commercializationofhigh-endperformancepa ckagingproducts Globalmappingofhigh-endperformancepackag ingsupplychain Supplyvaluechainanalysisinhigh-endperfor mancepackaging Application-technologyroadmapofhigh-endp erformancepackaging KeyPlayer stechnologyroadmapofhigh-endperformancep ackaging:Intel,TSMCandSamsung IPAnalysis:3 DSoC hybridbondingHigh-end Performance Packaging: 3 Integration 2020 | Sample | | 2020 KEY FEATURES OF REPORT6 High-End Performance Packaging.

4 3 Integration 2020 | Sample | | 2020 REPORT METHODOLOGIES & DEFINITIONSM arketVolume (in Munits)ASP (in $)Revenue (in $M)YoleD veloppement smarket forecast model is based on the matching of several sources:Information aggregationPreexistinginformation7 High-End Performance Packaging: 3 Integration 2020 | Sample | | 2020 ABOUT THE AUTHORB iographie& contactFavier SHOOF avier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole D veloppement, part of Yole Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the production of custom consulting 7 years at Applied Materials as a Customer Application Technologist in the advanced packaging marketspace, Favier developed an in-depth understanding of the supply chain and core business values. As an acknowledged expert in this field, Favier has provided training and held numerous technical review sessions with industry players.

5 In addition, he has obtained 2 to that, Favier worked at REC Solar as a Manufacturing Engineer to maximize production capacity. Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing holds a Bachelor s in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). Performance Packaging: 3 Integration 2020 | Sample | | 2020 ABOUT THE TEAMP ackaging, assembly and substrateFavierShooTechnology& MarketAnalystVaibhav TrivediSr. Technology& MarketAnalystSantosh Kumar PrincipalAnalystEmilie JolivetDivision DirectorSemiconductor& SoftwareExperience:8 years in Technology, Packaging and ManufacturingExperience: 17yearsin Emerging Semiconductorsand DevicesExperience15years in semiconductor industry Experience:12years in semiconductor industry At Yole:Packaging, Materials & ManufacturingAt Yole:Packaging, Assemblyand SubstratesAt Yole:Is Principal analyst for the division and analyst in packaging, assembly and substratesAt Yole:Manages Semiconductor and Software teamPreviouscompanies:Applied Materials, RECP reviouscompanies:Amkor, IntelPreviouscompaniesMK Electron, CCI IncPreviouscompanies:EV Group, Solarforce, FreescaleEducation:Bachelor in Materials Engineering (Hons)Minorin Entrepreneurship Education.

6 Materials Science and Materials Science and Engineering, Electronics in ElectronicMaterials9 ADI, AMD , Amkor, Annapurna/Amazon, ARM, ASE, Atmel, Broadcom/Avago, Broadpak, CEA-Leti, Cerebras, Cisco, Cray , Cypress, eSilicon, Facebook, Fraunhofer IZM, Freescale, Fujitsu, GlobalFoundries, Gloway, Google, Hitachi, HLMC, Huawei, Ibiden, IBM, IME, IMEC, Infineon, Intel, JCET, Juniper Networks, Kyocera, Micron, Mitsubishi, Nhanced, Nvidia, ON Semiconductor, Oracle, Panasonic, PTI, Qualcomm, Rambus, Renesas, Rohm, Samsung, Sanyo, SEMCO, Sharp, Shinko, SK hynix, Skywater, SMIC, Sony, SPIL, STMicroelectronics, Tesla, Tezzaron, TI, Toshiba, TSMC, UMC, Xilinx, Xperi, YMTCHigh-end Performance Packaging: 3 Integration 2020 | Sample | | 2020 COMPANIES CITED IN THIS REPORT10 SEMICONDUCTOR INDUSTRYC hronological order of players pursuing Moore s LawMoore s law has guided the global semiconductor industry for past decades (since 1965), improving both Performance and cost through node 2002 (130nm), the industry has been consolidating extensively.

7 Limitations in scaling has disrupted companies competing in this , it is an oligopoly market, with a handful of key players Performance Packaging: 3 Integration 2020 | Sample | | 20202618141410763320510152025130nm90nm65 nm45nm/40nm32nm/28nm22nm/20nm16nm/14nm10 nm7nm5nm/3nm2002-20032004-20062006-20082 008-20122010-20122012-20142014-20162017- 20192020-20222023-2025 Number of PlayersTechnology Node [Moore s Law*]YearADIAMDA tmelCypressFreescaleFujitsuHitachiHLMCIB MI nfineonIntelMitsubishiONPanasonicRenesas RohmSamsungSanyoSharpSMICSonySTMTIT oshibaTSMCUMCAMDC ypressFreescaleFujitsuIBMI nfineonIntelPanasonicRenesasSamsungSharp SMICSonySTMTIT oshibaTSMCUMCF ujitsuGFHLMCIBMI ntelPanasonicRenesasSamsungSMICSTMTIT oshibaTSMCUMCF ujitsuGFHLMCIBMI ntelPanasonicRenesasSamsungSMICSTMTIT oshibaTSMCUMCGFHLMCIBMI ntelPanasonicSamsungSMICSTMTSMCUMCI ntelSamsungTSMCGFI ntelSamsungSMICTSMCUMCI ntelSamsungTSMC??GFHLMCIBMI ntelSamsungSMICTSMC* Moore s law states that the number of transistors in an integrated circuit chips doubles every 2 yearsData referenced from Intel and WikiChipNumber of Players with leading-edge manufacturing capabilitiesOnly 3 players left[2020]11IC Substrate: BGA BallsIC Substrate: BGA BallsFan-Out (Core)Flip Chip: QFNFan-InFlip Chip: BumpFan-Out (HD FO)Fan-Out (UHD FO) Si InterposerFlip-Chip: bumps/Cu PillarsEmbedded Si bridge: bumps Flip-Chip: bumps/Cu PillarsFlip-Chip: bumps/Cu PillarsHybrid Bonding: BumplessHybrid Bonding.

8 Next-Gen1/mm22/mm24/mm28/mm216/mm232/mm2 64/mm2128/mm2256/mm2512/mm21024/mm22048/ mm24096/mm28192/mm216384/mm232768/mm2655 36/mm2131072/mm20,5 m1,0 m2,0 m4,0 m8,0 m16,0 m32,0 m64,0 m128,0 m256,0 m512,0 m1024,0 mI/O Density* ( I/O per mm2)Log ScaleIO Pitch ( m)Log ScaleIO Density vs IO Pitch (Log Scale) High-End Performance PackagingPresently, there is no acknowledged mainstream definition for high end Performance packaging within semiconductor distinct advanced packaging technologies, including flip-chip, embedded die, Si interposers, 3D-IC, fan-in, fan-out and hybrid bonding, are considered as High-End Performance packaging, then this will be over generalizing high end Performance packaging. This is because not all advanced packaging technology is high performing. For example, flip-chip and fan-out packaging can exist both in High-End and low-end order to prevent such confusion, YoleD veloppementclearly focuses and defines High-End Performance packaging based on IO density and IO --- High-End Performance packaging is defined as a forefront packaging technology, which value-adds device Performance with high IO Density ( 16/mm2) and fine IO Pitch ( 130 m)---TERMINOLOGY ---In this report, High-End Performance Packaging will be used interchangeable with High-End Packaging and HEP abbreviationHigh-end Performance Packaging.

9 3 Integration 2020 | Sample | | 2020 High-End Performance PACKAGING DEFINITIONYoleD veloppement sdefinition of High-End Performance packaging*I/O Density refers to total number of IOsper package platform areaPlot is generated based Yole D veloppement sand System Plus Consulting s database, with reference to industry average value and ,transistorcountsstillfollowtheguidanceo fMoore ,Manufacturingcostisstillbenefittingfrom Moore ,thedesigncosthasrisenmanytimes( ~35-40 Xcomparedto90nm)andmonolithicSoCmanufact uringhasbecomeextremelycomplex, , Performance Packaging: 3 Integration 2020 | Sample | | 2020 THE END OF MOORE'S LAW ?The pace has slowed down, if not the end2002200620102014201820221021031041051 06107180nm90nm45nm28nm14nm7nmMicroproces sor Performance (FLOPS)35 101 Transistor (k)Single thread performanceFrequency (MHz)Typical power (W)Number of cores20022006201020142018202230621252505 001,000180nm90nm45nm28nm14nm7nmDesign Cost ($M)35 1540nm $38M28nm $51M22nm $70M16nm $106M10nm $174M7nm $300M3nm $550M (?)

10 200220062010201420182022124816 Mfg Cost ( per Million Transistors ) Moore s /MTx90nm 10 /MTx7nm /MTx (?)90nm $15 MIn this report, we will be using the term slow down when describing the status of Moore s law13 High-End Performance Packaging: 3 Integration 2020 | Sample | | 2020 High-End Performance PACKAGING MARKET SEGMENTATIONThe market is divided into High-End & mid/low-end & 3D integrationHigh-end segmentHPCA rtificial IntelligenceData mining (crypto & other data)Super computersData centers, hyper scaleNetworkingSwitch / RouterGamingMid/Low-end segmentSensingMEMS & sensorsCISL ightingLEDHigh-end segment is defined as the market where an application is less sensitive to the cost, but requires reduced footprint in addition to high Performance & reliabilityMid/Low-end segment is defined by a good balance between cost sensitivity & & & & & & & & Infrastructure2019-2025 High-End Performance PACKAGING MARKET FORECAST20192025$ B$ BCAGR2019-2025=32% High-End Performance Packaging.


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