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High Voltage, Isolated Gate Driver with Internal Miller ...

High voltage , Isolated Gate Driver with Internal Miller Clamp, 2 A Output Data Sheet ADuM4121/ADuM4121-1. FEATURES GENERAL DESCRIPTION. 2 A peak output current (<2 RDSON) The ADuM4121/ADuM4121-11 are 2 A Isolated , single-channel V to V input drivers that employ Analog Devices, Inc.'s iCoupler technology V to 35 V output to provide precision isolation. The ADuM4121/ADuM4121-1. Undervoltage lockout (UVLO) at V VDD1 provide 5 kV rms isolation in the wide-body, 8-lead SOIC package. Multiple UVLO options on VDD2 Combining high speed CMOS and monolithic transformer Grade A: V (typical) UVLO on VDD2 technology, these isolation components provide outstanding Grade B: V (typical) UVLO on VDD2 performance characteristics superior to alternatives such as the Grade C: V (typical) UVLO on VDD2 combination of pulse transformers and gate drivers.

ranging from 2.5 V to 6.5 V, providing compatibility with lower voltage systems. In comparison to gate drivers that employ high voltage level translation methodologies, the ADuM4121/ ADuM4121-1 offer the benefit of true, galvanic isolation between the input and the output. The . ADuM4121/ADuM4121-1 include an internal Miller clamp

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Transcription of High Voltage, Isolated Gate Driver with Internal Miller ...

1 High voltage , Isolated Gate Driver with Internal Miller Clamp, 2 A Output Data Sheet ADuM4121/ADuM4121-1. FEATURES GENERAL DESCRIPTION. 2 A peak output current (<2 RDSON) The ADuM4121/ADuM4121-11 are 2 A Isolated , single-channel V to V input drivers that employ Analog Devices, Inc.'s iCoupler technology V to 35 V output to provide precision isolation. The ADuM4121/ADuM4121-1. Undervoltage lockout (UVLO) at V VDD1 provide 5 kV rms isolation in the wide-body, 8-lead SOIC package. Multiple UVLO options on VDD2 Combining high speed CMOS and monolithic transformer Grade A: V (typical) UVLO on VDD2 technology, these isolation components provide outstanding Grade B: V (typical) UVLO on VDD2 performance characteristics superior to alternatives such as the Grade C: V (typical) UVLO on VDD2 combination of pulse transformers and gate drivers.

2 Precise timing characteristics The ADuM4121/ADuM4121-1 operate with an input supply 53 ns maximum isolator and Driver propagation delay ranging from V to V, providing compatibility with lower CMOS input logic levels voltage systems. In comparison to gate drivers that employ high High common-mode transient immunity: >150 kV/ s voltage level translation methodologies, the ADuM4121/. High junction temperature operation: 125 C. ADuM4121-1 offer the benefit of true, galvanic isolation Default low output between the input and the output. Internal Miller clamp Safety and regulatory approvals (pending) The ADuM4121/ADuM4121-1 include an Internal Miller clamp UL recognition per UL 1577 that activates at 2 V on the falling edge of the gate drive output, 5 kV rms for 1-minute withstand supplying the driven gate with a lower impedance path to reduce CSA Component Acceptance Notice 5A the chance of Miller capacitance induced turn on.

3 VDE certificate of conformity (pending) Options exists to allow the thermal shutdown to be enabled or DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 disabled. As a result, the ADuM4121/ADuM4121-1 provide VIORM = 849 V peak reliable control over the switching characteristics of insulated Wide-body, 8-lead SOIC gate bipolar transistor (IGBT)/metal oxide semiconductor field, effect transistor (MOSFET) configurations over a wide range of APPLICATIONS. switching voltages. Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters Gallium nitride (GaN)/silicon carbide (SiC) power devices FUNCTIONAL BLOCK DIAGRAM.

4 VDD1 1. ADuM4121/ UVLO TSD. 8 VDD2. ADuM4121-1. DECODE. VI+ 2 ENCODE AND 7 VOUT. LOGIC. VI 3 6 CLAMP. 2V. GND1 4 5 GND2. 14967-001. UVLO. Figure 1. 1. Protected by Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

5 Tel: 2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support ADuM4121/ADuM4121-1 Data Sheet TABLE OF CONTENTS. Features .. 1 ESD Applications .. 1 Pin Configuration and Function General Description .. 1 Typical Performance Characteristics ..8. Functional Block Diagram .. 1 Theory of Operation .. 11. Revision History .. 2 Applications Information .. 12. 3 Printed Circuit Board (PCB) Layout .. 12. Electrical Characteristics .. 3 Propagation Delay-Related 12. Regulatory Information.

6 4 Undervoltage Lockout .. 12. Package Characteristics .. 4 Output Load Characteristics .. 13. Insulation and Safety-Related Specifications .. 5 Power 13. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Insulation Lifetime .. 14. Characteristics .. 5 Typical Applications .. 14. Recommended Operating Conditions .. 5 Outline Dimensions .. 16. Absolute Maximum Ratings .. 6 Ordering Guide .. 16. REVISION HISTORY. 10/2016 Revision 0: Initial Version Rev. 0| Page 2 of 16. Data Sheet ADuM4121/ADuM4121-1. SPECIFICATIONS. ELECTRICAL CHARACTERISTICS. Low-side voltages referenced to GND1.

7 High side voltages referenced to GND2; V VDD1 V; V VDD2 35 V, TJ = 40 C to +125 C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TJ = 25 C, VDD1 = V, VDD2= 15 V. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS. High Side Power Supply VDD2 Input voltage VDD2 35 V. VDD2 Input Current, Quiescent IDD2(Q) mA. Logic Supply VDD1 Input voltage VDD1 V. Input Current IDD1 5 mA VI+ = high, VI = low Logic Inputs (VI+, VI ). Input Current II+, II 1 +1 A.

8 Input voltage Logic High VIH VDD1 V V VDD1 5 V. V VDD1 > 5 V. Logic Low VIL VDD1 V V VDD1 5 V. V VDD1 > 5 V. UVLO. VDD1. Positive-Going Threshold VVDD1UV+ V. Negative-Going Threshold VVDD1UV V. Hysteresis VVDD1 UVH V. VDD2. Grade A. Positive Going Threshold VVDD2UV+ V. Negative Going Threshold VVDD2UV V. Hysteresis VVDD2 UVH V. Grade B. Positive Going Threshold VVDD2UV+ V. Negative Going Threshold VVDD2UV V. Hysteresis VVDD2 UVH V. Grade C. Positive Going Threshold VVDD2UV+ V. Negative Going Threshold VVDD2UV V. Hysteresis VVDD2 UVH V. Thermal Shutdown (TSD) The ADuM4121-1 does not have TSD.

9 Positive Edge TTSD_POS 155 C. Hysteresis TTSD_HYST 30 C. Internal NMOS Gate Resistance RDSON_N Tested at 250 mA, VDD2 = 15 V. Tested at 1 A, VDD2 = 15 V. Internal PMOS Gate Resistance RDSON_P Tested at 250 mA, VDD2 = 15 V. Tested at 1 A, VDD2 = 15 V. Internal Miller Clamp Resistance RDSON_MILLER 2 Tested at 200 mA, VDD2 = 15 V. Miller Clamp voltage Threshold VCLP_TH 2 V Referenced to GND2, VDD2 = 15 V. Peak Current IPK A VDD2 = 12 V, 4 gate resistance SWITCHING SPECIFICATIONS. Pulse Width PW 50 ns CL = 2 nF, VDD2 = 15 V, RGON 1 = RGOFF1 = 5 . Propagation Delay Rising Edge 2 tDLH 22 32 42 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5.

10 Falling Edge2 tDHL 30 38 53 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 . Rev. 0 | Page 3 of 16. ADuM4121/ADuM4121-1 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments Skew 3 tPSK 22 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 . Falling Edge 4 tPSKHL 12 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 . Rising Edge 5 tPSKLH 15 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 . Pulse Width Distortion tPWD 7 13 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 . Output Rise/Fall Time (10% to 90%) tR/tF 11 18 26 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 . Common-Mode Transient Immunity (CMTI) |CM|.


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