Low Noise Single-Ended to Differential

1 LT635016350fc For more information applicaTionDescripTionLow Noise Single-Ended to Differential Converter/ADC DriverThe LT 6350 is a rail-to-rail input and output low Noise Single-Ended to Differential converter/ADC driver featuring fast settling time. It converts a high or low impedance , Single-Ended input signal to a low impedance , balanced, Differential output suitable for driving high performance Differential succesive approximation register (SAR) ADCs. The two op amp topology features very low Noise op amps, that can support SNR >110dB in a 1 MHz input op amp is trimmed for constant low input-referred voltage offset over the input range to prevent VOS steps from degrading a single 5V supply, the outputs can swing from 55mV to With the addition of a negative supply, the LT6350 can swing from 0V to Output common mode voltage is set by applying a voltage to the +IN2 LT6350 draws from a 5V supply and consumes just 60 A in shutdown LT6350 is available in a compact 3mm 3mm, 8-pin leadless DFN package and also in an 8-pin MSOP package and operates over a 40 C to 125 C temperature Sine Wave, 1dBFS 8192-Point FFTFeaTuresapplicaTionsn Rail-to-Rail Input and Outputs n Fast Settling Time.

2 240ns, , 8VP-P Output Stepn Hz Input-Referred Op Amp Noisen High impedance Inputn 3dB Bandwidth: 33 MHzn to 12V Supply Operationn No External Gain Resistors Requiredn Supply Currentn Low Power Shutdownn Low Distortion (HD2/HD3): 102dBc/ 97dBc at 100kHz, VOUTDIFF = 4VP-Pn Low Offset Voltage: 400 V Maxn High DC Linearity: < 1 LSB, 16-Bit, 8VP-Pn Low Input Current Noise : Hzn 3mm 3mm 8-Pin DFN and 8-Lead MSOP Packagesn 16-Bit and 18-Bit SAR ADC Driversn Single-Ended to Differential Conversionn Differential Line DriverFREQUENCY (kHz)0 140 MAGNITUDE (dB) 30 10 20 60 50 40 70 80 90 110 100 120 13001002005003006350 TA02400V+ = 5V, V = 5 VVOUTDIFF = +IN2 = = = = = + +IN1 IN1V+V OUT2 OUT1 SHDN+IN2 VIN0V TO F499 2V 5 VLT63506350 TA01+ 249 249 2200pF+ AIN AIN+LTC2393-16 ADC Driver: Single-Ended Input to Differential OutputL, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation.

3 All other trademarks are the property of their respective owners. Protected by Patents including 5610557, more information conFiguraTionabsoluTe MaxiMuM raTingsTotal Supply Voltage (V+ V ) .. Current (Note 2) .. 20mAOutput Short-Circuit Current Duration(Note 3) ..IndefiniteOperating Temperature Range(Note 4) .. 40 C to 125 C(Note 1)TOP VIEWDD PACKAGE8-LEAD (3mm 3mm) PLASTIC DFN56784321 IN1+IN2V+OUT1+IN1 SHDNV OUT29 TJMAX = 150 C, JA = 43 C/W UNDERSIDE METAL CONNECTED TO V 1234 IN1+IN2V+OUT18765+IN1 SHDNV OUT2 TOP VIEWMS8 PACKAGE8-LEAD PLASTIC MSOPTJMAX = 150 C, JA = 250 C/WorDer inForMaTionLEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONSPECIFIED TEMPERATURE RANGELT6350 CDD#PBFLT6350 CDD#TRPBFLFJT8-Lead (3mm 3mm) Plastic DFN0 C to 70 CLT6350 IDD#PBFLT6350 IDD#TRPBFLFJT8-Lead (3mm 3mm) Plastic DFN 40 C to 85 CLT6350 HDD#PBFLT6350 HDD#TRPBFLFJT8-Lead (3mm 3mm)

4 Plastic DFN 40 C to 125 CLT6350 CMS8#PBFLT6350 CMS8#TRPBFLTFJV8-Lead Plastic MSOP0 C to 70 CLT6350 IMS8#PBFLT6350 IMS8#TRPBFLTFJV8-Lead Plastic MSOP 40 C to 85 CLT6350 HMS8#PBFLT6350 HMS8#TRPBFLTFJV8-Lead Plastic MSOP 40 C to 125 CConsult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping LTC Marketing for information on non-standard lead based finish more information on lead free part marking, go to: For more information on tape and reel specifications, go to: Temperature Range(Note 5) .. 40 C to 125 CMaximum Junction CStorage Temperature Range .. 65 C to 150 CLead Temperature (Soldering, 10 sec)MSOP Package Only ..300 C LT635036350fc For more information characTerisTicsSYMBOLPARAMETERCONDITIONS MINTYPMAXUNITSVOSDIFFD ifferential Input-Referred Offset VoltageVS = 5V V+IN1 = V2 = Mid-Rail V+IN1 = V2 = V + to V+ V+IN1 = V2 = V + to V+ l mV mV mVVS = 3V V+IN1 = V2 = V + to V+ V+IN1 = V2 = V + to V+ l mV mVVS = 10V V+IN1 = V2 = V + to V+ V+IN1 = V2 = V + to V+ l mV mVVOS1 Input Offset Voltage, Op Amp 1VS = 5V V+IN1 = V + to V+ V+IN1 = V to V+ l l mV mVVS = 3V V+IN1 = V + to V+ V+IN1 = V to V+ l l mV mVVS = 10V V+IN1 = V + to V+ V+IN1 = V to V+ l l mV mVVOS2 Input Offset Voltage, Op Amp 2 (Note 6)

5 VS = 3V, 5V, 10V V+IN1 = V2 = V + to V+ l mV VOSDIFF/ TDifferential Offset Voltage DriftV+IN1 = V2 = V + V+IN1 = V2 = V+ l5 V/ C V/ CIB1 Input Bias Current, Op Amp 1 (at +IN1, IN1)V+IN1 = Mid-Supply V+IN1 = V V+IN1 = V+l l l A A AIOS1 Input Offset Current, Op Amp 1 (at +IN1, IN1)V+IN1 = Mid-Supply V+IN1 = V V+IN1 = V+l l l 1 1 1 1 1 A A AI+IN2 Input Bias Current, Op Amp 2 (at +IN2)V+IN1 = V2 = AIOS2 Input Offest Current, Op Amp 2V2 = Mid-Supply Aen1 Input Voltage Noise Density, Op Amp 1Op Amp Input Hzin1 Input Current Noise Density, Op Amp Hzen2 Input Voltage Noise Density, Op Amp 2Op Amp Input Hzin2 Input Current Noise Density, Op Amp 21pA/ Hzen(OUT) Differential Output Noise Voltage DensityTotal Output Noise Including Both Op Amps and On-Chip Resistors. Input Shorted. f = HzInput Noise to 10Hz300nVP-PSNRO utput Signal-to- Noise RatioVOUTDIFF = 8VP-P, 1 MHz Noise Bandwidth110dBV+IN1 Input Voltage Range, +IN1 Guaranteed by CMRR1lV V+VV+IN2 Input Voltage Range, +IN2 Guaranteed by CMRR2lV + + ResistanceSingle-Ended Input at +IN14M The l denotes specifications that apply over the full specified temperature range, otherwise specifications are at TA = 25 C.

6 Unless noted otherwise, V+ = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V+, RL = OPEN, RF = SHORT, RG = OPEN. VS is defined as (V+ V ). VOUTCM is defined as (VOUT1 + VOUT2)/2. VOUTDIFF is defined as (VOUT1 VOUT2). See Figure more information characTerisTics The l denotes specifications that apply over the full specified temperature range, otherwise specifications are at TA = 25 C. Unless noted otherwise, V+ = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V+, RL = OPEN, RF = SHORT, RG = OPEN. VS is defined as (V+ V ). VOUTCM is defined as (VOUT1 + VOUT2)/2. VOUTDIFF is defined as (VOUT1 VOUT2). See Figure CapacitanceSingle-Ended Input at + Mode Rejection Ratio, Op Amp 1VS = 5V, V+IN1 = V IN1 = V + to V+ VS = 5V, V+IN1 = V IN1 = V + to V+ VS = 5V, V+IN1 = V IN1 = V to V+ VS = 3V, V+IN1 = V IN1 = V to V+ l l l82 77 72 6794 94 88 82dB dB dB dBCMRR2 Common Mode Rejection Ratio, Op Amp 2VS = 5V, V+IN1 = V2 = V + to V+ VS = 3V, V+IN1 = V2 = V + to V+ VS = 10V, V+IN1 = V2 = V + to V+ l l93 85 96118 110 118dB dB dBPSRRP ower Supply Rejection Ratio ( VS/ VOSDIFF)VS = to 12Vl80108dBVSS upply Voltage (Note 7) Balance ( VOUTDIFF/ VOUTCM) (Note 8)VOUTDIFF = 2Vl5068dBGAINC losed-Loop Gain ( VOUTDIFF/ (V+IN1 V2)) (V+IN1 V2) = 4Vl2V/VGAINERRC losed-Loop Gain Errorl GAINERR/ TClosed-Loop Gain Error Driftl3ppm/ CINLDC Linearity (Note 9)

7 V+ = 5V, V = 0V V+ = 5V, V = 2V V+ = 5V, V = 2V, 16-Bit, 8VP-P230 125 1 V V LSBRINTI nternal Resistors1000 VOHO utput Swing to V+, Either Output (Note 10)No Load Sourcing l55 360170 750mV mVVOLO utput Swing to V , Either Output (Note 10)No Load Sourcing l55 260170 460mV mVISCO utput Short-Circuit CurrentV+IN1 = Mid-Rail 200mV, V IN1 = Mid-Rail VS = 5V VS = 5V VS = 3V l l 27 15 15 45 45 40 mA mA mAVILSHDN Input Logic LowVS = to 12 VlV + Input Logic HighVS = to 12 VlV + Pin CurrentSHDN = V+ SHDN = V l l 1 45 201 A AISS upply CurrentVS = 3V VS = 5V VS = 5V VS = 10V l l mA mA mAIS(SHDN)Supply Current in ShutdownVS = 3V, VSHDN = VIL VS = 5V, VSHDN = VIL VS = 10V, VSHDN = VILl l l43 60 70220 240 260 A A AGBWGain-Bandwidth Product Frequency = 1 MHzOp Amp 1 (Noninverting) Op Amp 2 (Inverting)85 115 MHz MHzBWDifferential 3dB Small-Signal BandwidthVOUTDIFF = 100mVP-P VOUTDIFF = 100mVP-P l23 19 33 MHz MHzLT635056350fc For more information 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

8 Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and 2: Inputs are protected by diodes to each supply. Additionallly, op amp inputs +IN1, IN1 and +IN2 are protected by back-to-back diodes across the op amp inputs. If inputs are taken beyond the supplies or if either op amp s Differential input voltage exceeds , the input current must be limited to less than 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted 4: The LT6350C/LT6350I are guaranteed functional over the temperature range of 40 C to 85 C. The LT6350H is guaranteed functional over the temperature range of 40 C to 125 5: The LT6350C is guaranteed to meet specified performance from 0 C to 70 C. The LT6350C is designed, characterized and expected to meet specified performance from 40 C to 85 C, but is not tested or QA sampled at these temperatures.

9 The LT6350I is guaranteed to meet specified performance from 40 C to 85 C. The LT6350H is guaranteed to meet specified performance from 40 C to 125 6: VOS2 is measured as the total output common mode voltage offset (error between output common mode and voltage at V2). VOS2 includes the combined effects of op amp 2 s voltage offset, IB, IOS and mismatch between on-chip resistors and the 499 external resistor, R1 (See Figure 1).Note 7: Supply voltage range is guaranteed by the power supply rejection ratio 8: Output balance is calculated from gain error and gain as: BALGAINGAINERR= Note 9: DC linearity is measured by measuring the Differential output for each input in the set V+IN1 = , , , and calculating the maximum deviation from the least squares best fit straight line generated from the three data 10: Output voltage swings are measured between the output and power supply 11: Full- power bandwidth is calculated from the slew rate.

10 FPBW = SR/2 characTerisTics The l denotes specifications that apply over the full specified temperature range, otherwise specifications are at TA = 25 C. Unless noted otherwise, V+ = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V+, RL = OPEN, RF = SHORT, RG = OPEN. VS is defined as (V+ V ). VOUTCM is defined as (VOUT1 + VOUT2)/2. VOUTDIFF is defined as (VOUT1 VOUT2). See Figure Bandwidth (Note 11)VOUTDIFF = Load Drive, 20% OvershootNo Series Output Resistors56pFSRD ifferential Slew RateOUT1 Rising (OUT2 Falling) OUT1 Falling (OUT2 Rising)48 41V/ s V/ s HD2 HD310kHz DistortionVS = 5V, VOUTDIFF = 4VP-P, RL = 2k 2nd Harmonic 3rd Harmonic 115 115 dBc dBc HD2 HD3100kHz DistortionVS = 5V, VOUTDIFF = 4VP-P, RL = 2k 2nd Harmonic 3rd Harmonic 102 97 dBc dBc HD2 HD31 MHz DistortionVS = 5V, VOUTDIFF = 4VP-P, RL = 2k 2nd Harmonic 3rd Harmonic 86 75 dBc dBctSSettling Time to a 4V Input ( 1 LSB, 16-Bit, Falling Edge)