LTC1923 - High Efficiency Thermoelectric Cooler Controller

1 1 LTC19231923fHigh Efficiency ThermoelectricCooler ControllernHigh Efficiency , Low Noise TopologynAdjustable Output Slew Rate Reduces EMInFull-Bridge Controller for BidirectionalCurrent ControlnAdjustable Pulse-by-Pulse Bidirectional TECC urrent LimitnOpen/Shorted Thermistor IndicationnSolution Footprint in Less Than " "(Double-Sided PCB)nAvailable in 5mm x 5mm QFN and28-Pin SSOP PackagesnTEC Voltage ClampingnTEC Current, Voltage and Heat/Cool Status OutputsnAdjustable/Synchronizable Oscillator FrequencyReduces Filter Component Size and System Reference Voltage Minimum Operating Voltage, LTC and LT are registered trademarks of Linear Technology Fiber Optic LinksnMedical InstrumentsnCPU Temperature RegulatorsLaser Temperature Control Loop Achieving Setpoint Stability of CThe LTC 1923 is a pulse width modulator intended forthermoelectric Cooler (TEC) or heater applications requir-ing either unidirectional or bidirectional drive circuits.

2 Allof the necessary control circuitry and two sets of comple-mentary output drivers are integrated into the LTC1923 todrive a full bridge, providing an efficient means of bidirec-tional current flow to the TEC. An accurate temperaturecontrol loop to stabilize the temperature of a laser diodesystem is easily achieved with the addition of just a fewexternal components. Typical temperature setpoint accu-racy of C is achievable with the LTC1923 . Adding aninstrumentation amplifier front end allows setpoint stabil-ity of part features independent adjustable heating andcooling pulse-by-pulse current limit, current soft-start forcontrolled start-up, output slew rate control to reducesystem noise, differential current sense and voltage am-plifiers and a host of auxiliary circuits to protect the laserand provide redundant system +CS ITECTEC+TEC LTC1923 VDD +LTC2053A = F10 FL110 HVDDRSC1, C2: TAIYO YUDEN JMK325BJ226MM-T (X7R)L1, L2: SUMIDA CDRH6D2B-220NC*MNA, MPA: SILICONIX Si9801**MNB, MPB: SILICONIX Si98011923 F1 F10M100k10k1 FL210 HC122 FC222 FMPA*VREFMPB**MNA*MNB**TECCOOLER82kAPPLI CATIO SUFEATURESTYPICAL APPLICATIOUDESCRIPTIOU2 LTC19231923fVDD to GND.

3 To 6 VSDSYNC, to 6 VFB, CNTRL, VTHRM, ILIM, to 6 VCS+, CS , TEC+, TEC .. to 6 VORDER PARTNUMBERLTC1923 EGNTJMAX = 125 C, JA = 120 C/WABSOLUTE AXI U RATI GSWWWUPACKAGE/ORDER I FOR ATIOUUWThe l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25 = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise CHARACTERISTICS1234567891011121314 TOP VIEWGN PACKAGE28-LEAD PLASTIC SSOP2827262524232221201918171615 PLLLPFRSLEWSDSYNCCNTRLEAOUTFBAGNDSSILIMV SETFAULTVTHRMH/CVTECRTCTVREFPDRVBNDRVBVD DPGNDNDRVAPDRVACS+CS ITECTEC+TEC Consult LTC Marketing for parts specified with wider operating temperature ranges.(Note 1)FAULT, H/C .. to 6 VOperating Temperature Range (Note 2) .. 40 C to 85 CStorage Temperature Range .. 65 C to 125 CLead Temperature (Soldering, 10 sec) .. 300 CORDER PARTNUMBERLTC1923 EUH3231302928272625910111213141516171819 202122232487654321 CNTRLEAOUTFBAGNDNCSSILIMVSETPDRVBNDRVBVD DVDDPGNDNDRVAPDRVACS+SDSYNCRSLEWPLLLPFRT CTVREFNCNCFAULTVTHRMH/CVTECTEC TEC+ITECCS UH PACKAGE32-LEAD PLASTIC QFNPIN 1 TOP VIEWTJMAX = 125 C, JA = 34 C/WEXPOSED PAD IS PGND(MUST BE SOLDERED TO PCB)

4 SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITSI nput SupplyVDDO perating Supply LockoutLow to High to Lowl50130mVIDDO perating Supply CurrentNo Output Load, Outputs Not Switching24mAIDDSHDNS hutdown IDDSDSYNC = 0V1025 ASHDNTHS hutdown ThresholdMeasured at PDRVA, l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25 = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise CHARACTERISTICSSYMBOLPARAMETERCONDITIONS MINTYPMAXUNITSR eferenceVREFR eference Output VoltageNo Good ThresholdVREF Rising RegulationILOAD = 1mA to 10mA1025mVLINEREG Line RegulationVDD = to CurrentVREF = 0V1020mAOscillator and Phase-Locked LoopfOSCII nitial Oscillator FrequencyRT = 10k, CT = 330pF190225260kHzfOSCF requency VariationVDD = to 5V, CT = 330pF, RT = 10kl165225270kHzOSCPKCT Ramp Ramp Charge CurrentCT = , RT = 10k 150 ACTIDISCT Discharge CurrentCT = , RT = 10k150 APLLGAIN Gain from PLLLPF to RT Detector Output Current SinkingfSYNC < fOSC12 A SourcingfSYNC > fOSC 12 AMSTTHM aster Threshold On PLLLPF PinMeasured at SDSYNC PinVDD VDD Delay to Output2045 sError AmplifierVOSI nput Offset VoltageEAOUT = 1V, VCM = 1818mVAOLOpen-Loop GainEAOUT = to , CNTRL = Mode Input RangeEAOUT = + and CNTRL Input Bias CurrentsFB = CNTRL = 100100nAVOHO utput HighILOAD = 100 LowILOAD = 100 CurrentEAOUT = 1V, FB = , CNTRL = CurrentEAOUT = 1V, FB = 5V, CNTRL = Productf = 100kHz (Note 3)2 MHzCurrent Sense AmplifierACSA mplifier Gain10V/VCSOFFA mplifier OffsetMeasured at ITEC 15 210mVITECHO utput Sourcing Load RegulationCS+ - CS = 100mV, ILOAD = 0 to 50 Sinking Load RegulationCS+ - CS = 100mV, ILOAD = 0 to 50 3dB Frequency(Note 3)

5 500kHzILIMTHC urrent Limit ThresholdMeasured at CS+, CS l125145165mVILIMDLYC urrent Limit Delay to Output300450nsSSICHGSoft-Start Charge CurrentSS = ASSILIMSoft-Start Current Limit ThresholdSS = , Measured at CS+, CS 507090mVILIMILIM Current Limit ThresholdILIM = , Measured at CS+, CS 507090mV4 LTC19231923fNote 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be 2: The LTC1923E is guaranteed to meet specifications from 0 C to70 C. Specifications over the 40 C to 85 C operating temperature rangeare assured by design, characterization and correlation with statisticalprocess CHARACTERISTICSNote 3: Guaranteed by design, not tested in l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25 = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise Voltage AmplifierATECA mplifier OffsetMeasured at VTEC, VCM = 7mVTECCMRC ommon Mode < VCM < High VoltageILOAD = 50 Low VoltageILOAD = 50 3dB Frequency(Note 3)

6 1 MHzOutput DriversOUTHO utput High VoltageIOUT = Low VoltageIOUT = Rise TimeCLOAD = 1nF20nstFALLO utput Fall TimeCLOAD = 1nF20nstrSLEWO utput Rise TimeCLOAD = 1nF, RSLEW = 10k20nstfSLEWO utput Fall TimeCLOAD = 1nF, RSLEW = 10k20nstrSLEWO utput Rise TimeCLOAD = 1nF, RSLEW = 100k90nstfSLEWO utput Slew Fall TimeCLOAD = 1nF, RSLEW = 100k90nsSLEWVTRSLEW Disable Dead TimeRT = 10k90nsFaultOPENTHOpen Thermistor ThresholdVSET = 5V, Measured with Respect to VSET 410mVSHRTTHS horted Thermistor ThresholdVSET = 5V, Measured with Respect to Output Low Voltage1mA Into FAULT, During Fault150300mVDirection ComparatorDIRHLow-to-High ThresholdTEC = , Measured with Respect to TEC 50mVSensed When H/C Toggles LowDIRLHigh-to-Low ThresholdTEC = , Measured with Respect to TEC 50mVSensed When H/C Toggles HighHCVH/C Output Low Voltage1mA Into Pin150300mV5 LTC19231923fTEMPERATURE ( C) 50165 OSCILLATOR FREQUENCY (kHz)185205225265 201040701923 G01100130245CT = 330pFRT = 10kRT (k )50 OSCILLATOR FREQUENCY (kHz)20060080010001518001923 G024001020120014001600CT = 68pFCT = 150pFCT = 330pFVDD = , 5 VTA = 25 CTEMPERATURE ( C)VREF (V) 50 20104070100130 TYPICAL PERFOR A CE CHARACTERISTICS UWVREF vs IREF for DifferentTemperaturesOutput Dead Time vs RTError Amplifier Offset Voltagevs TemperatureOpen Thermistor Thresholdvs TemperatureOutput Rise/Fall Time vs RSLEWS horted Thermistor Thresholdvs TemperatureIREF (mA)0 VREF (V) G04515TA = 125 CTA = 25 CTA = 50 CRT (k )5 DEAD TIME (ns)125151923 = = 5 VTA = 25 C0 RISE TIME (ns)1001501923 G06500100200300250200 RSLEW (k )TA = 25 CTEMPERATURE ( C) 50 AMPLIFIER VIO (mV) 201040701923 G07100130 TEMPERATURE ( C) THERMISTOR THRESHOLD (V) 201040701923 G08100130 VSET = 5 VTEMPERATURE ( C) THERMISTOR THRESHOLD (V)

7 201040701923 G09100130 VSET = 5 VOscillator Frequencyvs TemperatureOscillator Frequency vs RTVREF vs Temperature6 LTC19231923fTYPICAL PERFOR A CE CHARACTERISTICS UWRepresentative Waveforms for NDRVA,NDRVB, TEC Current and CS+ CS Representative Waveforms forTEC Current, CS+ CS and ITECVDD = 5V1923 = RS = CH1: TEC CURRENT (500mA/DIV)CH2: VOLTAGE SENSE RESISTOR(CS+ CS ) 100mV/DIVCH3: NDRVA (5V/DIV)CH4: NDRVB (5V/DIV)CH2: VOLTAGE ACROSS SENSERESISTOR RS (CS+ CS ) 100mV/DIVCH3: VOLTAGE ON ITEC PIN EQUAL TOTEN TIMES THE ABSOLUTE VALUE OFCH2 (200mV/DIV)CH1: TEC CURRENT (500mA/DIV)CH1, CH3CH2 VDD = 5V1923 = RS = System Power Lossvs TEC CurrentTEC Clamp Voltagevs TemperatureCurrent Limit Thresholdvs TemperatureTEMPERATURE ( C) 50 CURRENT LIMIT THRESHOLD (mV)1301923 G10 20401070100165160155150145140135130125 TEC CURRENT (A) LOSS (W)VDD = 5 VVDD = = 25 CTEMPERATURE ( C) 50 TEC CLAMP VOLTAGE (V)1301923 G12 Test Conditions as Above, Except in Heating Mode.

8 TEC s Higher Heating Mode EfficiencyResults in Higher Thermal Gain. C Peak-to-Peak Variation Is 4x Stability Tilt, Just Detectable, Shows Similar 4x Improvement vs AboveLong-Term Cooling Mode Stability Measured in Environment that Steps 20 Degrees Above AmbientEvery Hour. Data Shows Resulting C Peak-to-Peak Variation, Indicating Thermal Gain of2500. C Baseline Tilt Over Plot Length Derives From Varying Ambient Temperature1923 PERFOR A CE CHARACTERISTICS UW8 LTC19231923fUUUPI FU CTIO SPLLLPF (Pin 1/Pin 30): This pin serves as the lowpassfilter for the phase-locked loop when the part is beingsynchronized. The average voltage on this pin equallyalters both the oscillator charge and discharge currents,thereby changing the frequency of operation. Bringing thevoltage on this pin above VDD signifies that the partwill be used as the synchronization master. This allowsmultiple devices on the same board to be operated at thesame frequency.

9 The SDSYNC pin will be pulled low duringeach CT charging cycle to facilitate (Pin 2/Pin 31): Placing a resistor from this pin toAGND sets the voltage slew rate of the output driver minimum resistor value is 10k and the maximumvalue is 300k. Slew rate limiting can be disabled by tyingthis pin to VDD, allowing the outputs to transition at theirmaximum (Pin 3/Pin 32): This pin can be used to disable theIC, synchronize the internal oscillator or be the master tosynchronize other devices. Grounding this pin will disableall internal circuitry and cause NDRVA and NDRVB to beforced low and PDRVA and PDRVB to be forced to will be forced low. FAULT will also be asserted lowindicating a fault condition. The pin can be pulled low forup to 20 s without triggering the shutdown circuitry. Thepart can either be slaved to an external clock or can be usedas the master (see Applications Information for a moredetailed explanantion).CNTRL (Pin 4/Pin 1): Noninverting Input to the (Pin 5/Pin 2): Output of the Error Amplifier.

10 Theloop compensation network is connected between this pinand FB. The voltage on this pin is the input to the PWMcomparator and commands anywhere between 0% and100% duty cycle to control the temperature of the tem-perature sense (Pin 6/Pin 3): The Inverting Input to the Error input is connected to EAOUT through a compensatingfeedback (Pin 7/Pin 4): Signal Ground. All voltages aremeasured with respect to AGND. Bypass VDD and VREF with low ESR capacitors to the ground plane near this (Pin 8/Pin 6): The TEC current can be soft-started byadding a capacitor from this pin to ground. This capacitorwill be charged by a A current source. This pin connectsto one of the inverting inputs of the current limit compara-tor and allows the TEC current to be linearly ramped up fromzero. The voltage on this pin must be greater than toallow the open/shorted thermistor window comparitor tosignal a (Pin 9/Pin 7): A voltage divider from VREF to this pinsets the current limit threshold for the TEC.