MCP39F501 Data Sheet - Microchip Technology

1 2013 Microchip Technology 1 MCP39F501 Features: Power Monitoring Accuracy capable of error across 4000:1 dynamic range Fast Calibration Routines Programmable Event Notifications such as over-current and voltage sag, surge protection 512 bytes User-accessible EEPROM through page read/write commands Non-volatile On-chip Memory, no external memory required Built-in calculations on fast 16-bit processing core- Active, Reactive and Apparent Power- True RMS Current, RMS Voltage- Line Frequency, Power Factor Two-Wire Serial Protocol using a 2-wire Universal Asynchronous Receiver/Transmitter (UART) inter-face supporting multiple devices on a single bus Low-Drift Internal Voltage Reference, 10 ppm/ C typical 28-lead 5x5 QFN package Extended Temperature Range -40 C to +125 CApplications: Real-time Measurement of Input Power for AC/DC supplies Intelligent Power Distribution UnitsDescription:The MCP39F501 is a highly integrated, single-phasepower-monitoring IC designed for real-timemeasurement of input power for AC/DC powersupplies, power distribution units and industrialapplications.

2 It includes dual-channel delta sigmaADCs, a 16-bit calculation engine, EEPROM and aflexible 2-wire interface. An integrated low-drift voltagereference with 10 ppm/ C in addition to dB ofSINAD performance on each measurement channelallows for better than accurate designs across a4000:1 dynamic Type Functional Block Diagram 12523458910 11 12212019181728272624 MODE/DIRNCUART_RXCOMMONANCNCNCAVDDUART_T XRESETDVDDDGNDMCLREP2967 OSCIOSCO13 14 COMMONBA0/DIO016152322 REFIN+/OUTDIO3I1+I1-V1-V1+AN_IN/DIO2 AGNDDGNDA1/DIO1 DRMCP39F5015x5 QFN** Includes Exposed Thermal Pad (EP); see Table Delta Sigma Multi-level+-SINC3 Digital FilterModulator ADC PGA I1+I1-24-bit Delta Sigma Multi-level+-SINC3 Digital FilterModulator ADC PGA V1+V1-16-BITCOREC alculationEngine (CE)

3 ConfigurableDigital OutputsUARTS erialInterfaceUART_TXUART_RXA0/DIO0 FLASH 10-bit SARADCAN_IN/DIO2 OSCIOSCOT iming GenerationInternalOscillatorGenerationAV DDAGNDDVDDDGNDA1/DIO1 MODE/DIRDIO3AN_IN/DIO2 Single-Phase, Power-Monitoring IC with Calculation and Event DetectionMCP39F501DS20005256A-page 2 2013 Microchip Technology Typical Application Single Phase, Two-Wire Application Schematic DGNDOSCOOSCIDVDDRESETAVDDI1+I1-V1-V1+NCN CNCREFIN/OUT+AGNDCOMMONA,BNCLOAD+ + +-33 nF33 nF33 nF1k 1k 1k 720 k 1k 4 MHz22 pF22 pF33 F470 470 F10 1 m 1m TEMPIN/DIO22m Leave MCP9700A(OPTIONAL)+ MCU UARTto MCU UARTUART_RXUART_TXDR(OPTIONAL)Connect on PCBA0/DIO0 DIO3A1/DIO1 MODE/DIRDIO2 Address setting for multiple devicesorAlarm with Event FunctionsMCP39F5014m 2013 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings to to inputs and outputs to Inputs (I+,I-,V+,V-).

4 -2V to +2 VVREF input to AVDD + Current out of DGND mAMaximum Current into DVDD mAMaximum Output Current Sunk by Digital IO ..25 mAMaximum Current Sourced by Digital mAStorage temperature ..-65 C to +150 CAmbient temperature with power C to +125 CSoldering temperature of leads (10 seconds) .. +300 CESD on the analog inputs (HBM,MM) .. kV, 200 VESD on all other pins (HBM,MM) .. kV, 200V Notice: Stresses above those listed under MaximumRatings may cause permanent damage to the is a stress rating only and functional operation ofthe device at those or any other conditions above thoseindicated in the operation listings of this specification isnot implied.

5 Exposure to maximum rating conditions forextended periods may affect device TABLE 1-1:ELECTRICAL CHARACTERISTICSE lectrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = to V, TA = -40 C to +125 C, MCLK = 4 MHz, PGA GAIN = ConditionsPower MeasurementActive Power (Note 2)P %4000:1 Dynamic Range on Current Channel (Note 1)Reactive Power (Note 2)Q %4000:1 Dynamic Range on Current Channel (Note 1)Apparent Power (Note 2)S %4000:1 Dynamic Range on Current Channel (Note 1)Current RMS (Note 2)IRMS %4000:1 Dynamic Range on Current Channel (Note 1)Voltage RMS (Note 2)VRMS %4000:1 Dynamic Range on Voltage Channel (Note 1)Power Factor (Note 2) %Line Frequency (Note 2)VRMS %Calibration, Calculation and Event Detection TimesAuto-Calibration TimetCAL 2Nx(1/fLINE) msNote 7 Minimum Calculationand Event Detection TimetCALC_EVENT2Nx(1/fLINE) msMinimum Time for Voltage Sag DetectiontAC_DROP see Section msNote 4 Note 1:Specification by design and characterization; not production :Calculated from reading the register :VIN=1 VPP= 353 mVRMS@ 50/60 :Applies to Voltage Sag and Voltage Surge Events :Variation applies to internal clock and UART only.

6 All calculated output quantities are temperature compensated to the performance listed in the respective :Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section Typical Performance Curves for typical :N = Value in the AccumulationInternalParameter register (0x005A). The default value of this register is 2 or TCAL=80ms for 50 Hz 4 2013 Microchip Technology Delta Sigma ADC PerformanceAnalog Input Absolute Voltage VIN-1 +1 VAnalog Input Leakage CurrentAIN 1 nADifferential Input Voltage Range(I1+ I1-),(V1+ V1-)-600/GAIN +600/GAINmVVREF = , proportional to VREFO ffset Error VOS-1 +1mVOffset Error Drift V/ CGain ErrorGE-4 +4%Note 6 Gain Error Drift 1 ppm/ CDifferential Input ImpedanceZIN232 k G=1142 k G=272 k G=438 k G=836 k G=1633 k G=32 Signal-to-Noise and Distortion dBNote 3 Total Harmonic DistortionTHD 3 Signal-to-Noise RatioSNR9295 dBNote 3 Spurious Free Dynamic RangeSFDR 111 dBNote 3 CrosstalkCTALK -122 dBAC Power Supply Rejection RatioAC PSRR -73 dBAVDD and DVDD= + , 100 Hz, 120 Hz.

7 1 kHzDC Power Supply Rejection RatioDC PSRR -73 dBAVDD and DVDD= to Common Mode Rejection RatioDC CMRR -105 dBVCM varies from -1V to +1V10-Bit SAR ADC Performance for Temperature MeasurementResolutionNR 10 bitsAbsolute Input DGND+ Impedance of Analog Voltage SourceRIN Integral Non-LinearityINL 1 2 LSbTABLE 1-1:ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = to V, TA = -40 C to +125 C, MCLK = 4 MHz, PGA GAIN = ConditionsNote 1:Specification by design and characterization; not production :Calculated from reading the register :VIN=1 VPP= 353 mVRMS@ 50/60 :Applies to Voltage Sag and Voltage Surge Events :Variation applies to internal clock and UART only.

8 All calculated output quantities are temperature compensated to the performance listed in the respective :Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section Typical Performance Curves for typical :N = Value in the AccumulationInternalParameter register (0x005A). The default value of this register is 2 or TCAL=80ms for 50 Hz line. 2013 Microchip Technology 5 MCP39F501 Differential Non-LinearityDNL 1 ErrorGERR 1 3 LSbOffset ErrorEOFF 1 2 LSbTemperature Measurement Rate fLINE/2N spsNote 7 Clock and TimingsUART Baud RateUDB kbpsSee Section for protocol detailsMaster Clock and Crystal FrequencyfMCLK-2%4+2%MHzCapacitive Loading on OSCO pinCOSC2 15pFWhen an external clock is used to drive the deviceInternal Oscillator To l e r a n c efINT_OSC 2 %-40 to +85 C only (Note 5)

9 Internal Voltage ReferenceInternal Voltage Reference ToleranceVREF-2% +2%VTemperature CoefficientTCVREF 10 ppm/ CTA = -40 C to +85 C, VREFEXT = 0 Output ImpedanceZOUTVREF 2 k Current, VREFAIDDVREF 40 AVoltage Reference InputInput Capacitance 10pFAbsolute Voltage on VREF+ PinVREF+AGND+ AGND+ SpecificationsOperating VoltageAVDD, Start Voltage to Ensure Internal Power-On Reset SignalVPORDGND Rise Rate to Ensure Internal Power-On Reset V/ms0 in , 0 in 60 msAVDD Start Voltage to Ensure Internal Power-On Reset SignalVPORAGND Rise Rate to Ensure Internal Power On Reset V/ms0 in 50 msTABLE 1-1:ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = to V, TA = -40 C to +125 C, MCLK = 4 MHz, PGA GAIN = ConditionsNote 1:Specification by design and characterization; not production :Calculated from reading the register :VIN=1 VPP= 353 mVRMS@ 50/60 :Applies to Voltage Sag and Voltage Surge Events :Variation applies to internal clock and UART only.

10 All calculated output quantities are temperature compensated to the performance listed in the respective :Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section Typical Performance Curves for typical :N = Value in the AccumulationInternalParameter register (0x005A). The default value of this register is 2 or TCAL=80ms for 50 Hz 6 2013 Microchip Technology Inc. Operating CurrentIDD 13 mAData EEPROM MemoryCell EnduranceEPS100,000 E/WSelf-Timed Write Cycle TimeTIWD 4 msNumber of Total Write/Erase Cycles Before RefreshRREF 10,000,000 E/WCharacteristic RetentionTRETDD40 Years Provided no other specifications are violatedSupply Current during ProgrammingIDDPD 7 mATABLE 1-2:SERIAL DC CHARACTERISTICSE lectrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = to V, TA = -40 C to +125 C, MCLK = 4 ConditionsHigh-Level Input DVDD DVDDVLow-Level Input VoltageVILVSS Output VoltageVOH3 VIOH= , VDD= Output VoltageVOL mA, VDD= Leakage CurrentILI 1 A ADIO pins onlyTABLE 1-3.