MOS VLSI DESIGN - Purdue Engineering

1 MOS vlsi DESIGN KAUSHIK ROY EDWARD G. TIEDEMANN JR. DISTINGUISHED PROFESSOR ECE, Purdue UNIVERSITY Prof. Kaushik Roy @ Purdue Univ. Grading Policy Source: Intel Prof. Kaushik Roy @ Purdue Univ. Mid-terms + quizzes + hw will account for 75% of the grade 3 mid-terms Mandatory and has to be taken on the scheduled day of the exam. Project will account for 25% of the grade. Late projects will not be accepted. You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above. Any form of cheating will be heavily penalized and reported to the Dean of students and may result in a failing grade. Instructor reserves right to change project requirements. Text and References Source: Intel Prof. Kaushik Roy @ Purdue Univ. Text: Digital Integrated Circuits: A DESIGN Perspective, J.

2 Rabaey et. al., Prentice Hall, Second edition References: Principles of CMOS vlsi DESIGN : A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley Circuits, Interconnects, and Packaging for vlsi , H. Bakoglu, Addison Wesley Class Notes: ~ vlsi /ee559/2013 Conferences & Journals Source: Intel Prof. Kaushik Roy @ Purdue Univ. IEEE Transactions on vlsi Systems IEEE Transactions on Electron Devices Electron Device Letters IEEE Transactions on nanotechnology IEEE Transactions on CAD of IC s IEEE Journal of Solid State Circuits IEEE vlsi Circuits Symposium Journal of Electronic Testing ACM DESIGN Automation Conference IEEE International Conference on CAD IEEE Solid State Circuits Conference International symposium on Low-Power Electronics & DESIGN IEEE Conference on Computer DESIGN IEEE International Test Conference Course Outline Source: Intel Prof.

3 Kaushik Roy @ Purdue Univ. Introduction: Historical perspective and Future Trend Semiconductor Devices On-current, Off-current, Short-channel effects and how it impacts DESIGN , transistor parameter variations; technology directions (Bulk, Multi-gate transistors) CMOS Logic: Basic CMOS logic gates and different logic styles (Ratioed logic, Standard CMOS, Domino, DCVS, ..); Inverter transfer characteristics, static and dynamic behavior, power and energy consumption of static MOS inverters; scaling implications; designing for low-leakage; Implications of different transistor technologies (Bulk, SOI, double/tri-gates) on circuit DESIGN Course Outline (Cont d) Source: Intel Prof. Kaushik Roy @ Purdue Univ. Low Voltage Low Power Logic Near-threshold logic operation, designing for low-leakage current On-chip memory DESIGN in scaled technologies: Different FF s, 6-T SRAM bit-cells (stability analysis: read, write, hold, access under parameter variations), robust DESIGN of 6-T SRAMs, Bit-cells for low voltage and low-leakage (6-T, 8-T configurations and analysis); technology considerations (Bulk versus Multi-gate) Technology directions high density on-chip magnetic memories Interconnect and timing issues DESIGN of circuits in CMOS and other emerging technologies and circuit evaluation using PETE (in the nanohub) vlsi CAD Lab and TA Source: Intel Prof.

4 Kaushik Roy @ Purdue Univ. vlsi CAD Lab located in 360 Potter SUN workstations running Cadence and Synopsys tools Courtesy key for after-hour access can be obtained from front desk in Potter Engineering Library Additional workstations in MSEE 186 Lab TA: Facilitates the use of lab DESIGN tools. Office hours: TBA Lab Orientation will be held in the second week Lab URL ~ Course Project Source: Intel Prof. Kaushik Roy @ Purdue Univ. Complete DESIGN of a functional logic block or system Complexity of 5000+ transistors DESIGN using the CADENCE tools and HSPICE DESIGN your own library from scratch Functionality to be verified Critical path timing should be verified using HSPICE Project report due the last day of class Project presentation by each group in the last week of class Work in a group of 2 will be allowed in special cases Start early!

5 Emphasis on power dissipation, performance, reconfigurability, low voltage DESIGN A Historical Perspective and Future Trends Prof. Kaushik Roy @ Purdue Univ. References: Adapted from: Digital Integrated Circuits: A DESIGN Perspective, J. Rabaey UCB Principles of CMOS vlsi DESIGN : A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian The First Computer Source: Intel Prof. Kaushik Roy @ Purdue Univ. The Babbage Differential Engine (1834) 25,000 mechanical parts Cost 17,470 Digital Electronic Computing Source: Intel Prof. Kaushik Roy @ Purdue Univ. Started with the introduction of vacuum tube ENIAC for computing artillery firing tables in 1946 Integration density 80 feet long, feet high, and several feet wide 18,000 vacuum tubes Reliability issues and excessive power consumption Did not go far until the invention of the transistor at Bell Lab in 1947 HISTORY Source: Intel Prof.

6 Kaushik Roy @ Purdue Univ. MOS field-effect transistor: Lilienfeld (1925), Heil (1935) Bipolar transistors: Bardeen (1947), Schockley (1949) First Bipolar digital logic: Harris (1956) IC Logic family: Transistor-Transistor Logic (TTL) (1962) Emitter-Coupled Logic (ECL) (1971) Integrated Injection Logic (I2L) (1972) PMOS and NMOS transistors on the same substrate: Weimer (1962), Wanlass (1965) PMOS-only logic until 1971 when NMOS technology emerged NMOS-only logic until late 1970s, when CMOS technology took over Later developments: BiCMOS, GaAs, low-temperator CMOS, super-conducting technologies, Nano-electronic Chip Complexity Source: Intel Prof. Kaushik Roy @ Purdue Univ. Clock Frequency Source: Intel Prof. Kaushik Roy @ Purdue Univ. Core Count Source: Intel Prof.

7 Kaushik Roy @ Purdue Univ. Total Die on Cache Source: Intel Prof. Kaushik Roy @ Purdue Univ. Intel 4004 Microprocessor Source: Intel Prof. Kaushik Roy @ Purdue Univ. Intel Pentium (II) Microprocessor Source: Intel Prof. Kaushik Roy @ Purdue Univ. Technology Scaling Source: Intel Prof. Kaushik Roy @ Purdue Univ. Technology scaling improves: Transistor & interconnect performance Transistor density Energy consumed per switching transition scaling factor (30% scaling) results in: 30% gate delay reduction (43% freq. ) 2X transistor density increase (49% area ) Energy per transition reduction Technology Scaling Source: Intel Prof. Kaushik Roy @ Purdue Univ. reduction)delay (30% )(,, == == = scalesddscalesddscalestddscalestscalesdd scaleCVEICVDVVTkWIVVD imensionsoxExponential Increase in Leakage Prof.

8 Kaushik Roy @ Purdue Univ. Non-Silicon Technology Silicon Micro- electronics Silicon Nano- electronics 1970 1980 2000 2010 2020 Junction leakage Gate Source n+ n+ Bulk Drain Subthreshold Leakage Gate Leakage A. Grove, IEDM 2002 Leakage Power (% of Total) 0% 10% 20% 30% 40% 50% Must stop at 50% 610 ONOFFII=310 ONOFFII=2~6~ 10 ONOFFII1 m 100 nm 10 nm 5 m Technology Trend Prof. Kaushik Roy @ Purdue Univ. Buried Oxide (BOX)SubstrateFully-depleted bodyGateVGVSVDD rainSourceVbackBuried Oxide (BOX)SubstrateFully-depleted bodyGateVGVSVDD rainSourceVbackBulk-CMOS FD/SOI Nano devices Carbon nanotube Graphene TFETs III-V devices Spintronics Single gate device 2009 2020 DGMOS FinFET Trigate Multi-gate devices Buried Oxide (BOX)SubstrateSourceFloating BodyDrainGateVSVGVDB uried Oxide (BOX)SubstrateSourceFloating BodyDrainGateVSVGVDPD/SOI DESIGN methods to exploit the advantages of technology innovations Variation in Process Parameters Source: Intel Prof.

9 Kaushik Roy @ Purdue Univ. Inter and Intra-die Variations Device parameters are no longer deterministic Device 1 Device 2 Channel length Delay and Leakage Spread 10 100 1000 10000 1000 500 250 130 65 32 Technology Node (nm) # dopant atoms Source: Intel Random dopant fluctuation Reliability Prof. Kaushik Roy @ Purdue Univ. Temporal degradation of performance: NBTI, HCI, TDDB Tech. generation Failure probability Time Defects Life time degradation Power & Power Density Prof. Kaushik Roy @ Purdue Univ. Year Power (Watts) P6 Pentium proc 486 386 286 8086 8085 8080 8008 4004 1 10 100 1971 1974 1978 1985 1992 2000 Power Density (W/cm2) Year Increased Average Power Battery Life Cooling Cost Increased Power Density Reliability Source: Intel Supply Voltage & Transistor Threshold Voltage Source: Intel Prof.

10 Kaushik Roy @ Purdue Univ..35 .25 .18 Technology Generation ( m)01234501234567 VCC or VT (V)VT=.45 VVCC= (VCC- VT)Gate over driveVCC or VT (V)543210 Voltage scaling is good for controlling IC s active power, but it requires aggressive VT scaling for high performance Barriers to Voltage Scaling Source: Intel Prof. Kaushik Roy @ Purdue Univ. Technology Generation Subthreshold Leakage 1 10 100 1000 constrained Ioff maintain Vcc/Vt Leakage power Short-channel effects Soft error Delay Source: Intel Prof. Kaushik Roy @ Purdue Univ. 2 W W 1 . = + CL T ox V DD V T V DD n p 0 5 0 5 0 3 0 9 1 3 2 .. ( . ) . ( ) [1] [1] C. Hu, Low Power DESIGN Methodologies, Kluwer Academic Publishers, p. 25. DDDLdIVC= 2)1()2(DDTDDoxLdVVVCLWC = )1(DDTSAToxLdVVWCC = Long Channel MOSFET Short Channel MOSFET Performance significantly degrades when VDD approaches 3VT.