MPC5744P Data Sheet - NXP

1 MPC5744 PMPC5744P data Sheet32-bit MCU suitable for ISO26262 ASIL-D chassis and safety applicationsFeatures The MPC5744P microcontroller is based on the PowerArchitecture developed by NXP. It targets chassisand safety applications and other applications requiringa high Automotive Safety Integrity Level (ASIL). TheMPC5744P is a SafeAssure solution. This document provides electrical specifications, pinassignments, and package diagram information for theMPC5744P series of microcontroller units (MCUs).For functional characteristics and the programmingmodel, see the MPC5744P Reference Manual. Junction temperature: The upper limit is 150 C or165 C depending on the device SemiconductorsDocument Number MPC5744 PData Sheet : Technical DataRev. , 11/2017 NXP reserves the right to change the production detail specifications as may berequired to permit improvements in the design of its of pinouts and descriptions.

2 Startup and reset supply and reference voltage input C junction temperature maximum operating notes for specifications at maximumjunction compatibility (EMC).. discharge (ESD) regulator electrical electrical current oscillator electrical electrical MHz Internal RC Oscillator (IRCOSC) electrical memory junction temperature 150 junction temperature 165 memory read wait-state and address-pipelinecontrol electrical sequence pad (EXT_POR, RESET) interrupt timing (IRQ pin).. switching package revision data Sheet , Rev. , 11/20172 NXP following table summarizes the features of the 1. MPC5744P feature summaryFeatureDetailsCPUP ower Architecture2 x e200z4 in delayed lock stepArchitectureHarvardExecution speed0 MHz to 200 MHz (+2% FM)Embedded FPUYesCore MPU24 regionsInstruction Set PPCNoInstruction Set VLEYesInstruction cache8 KB, EDCData cache4 KB, EDCData local memory64 KB, ECCS ystem MPUYes (16 regions)BusesCore busAHB, 32-bit address, 64-bit data , e2e ECCI nternal periphery bus32-bit address, 32-bit dataCrossbarMaster x slave ports4 x 5 Memory see Table 2 for additional detailsCode/ data flash MB, ECC, RWWData flash memorySupported with RWWSRAM384 KB, ECCO verlay access to SRAM from Flash Memory ControllerYesModulesInterrupt controller32 interrupt priority levels, 16 SW programmable interruptsPIT1 module with 4 channelsSystem Timer Module (STM)

3 1 module with 4 channelsSoftware Watchdog Timer (SWT)YeseDMA32 channels, in delayed lock stepFlexRay1 module with 64 message buffer, dual channelFlexCAN3 modules with 64 message bufferLINFlexD (UART and LIN with DMA support)2 modulesTable continues on the next data Sheet , Rev. , 11/2017 NXP Semiconductors3 Table 1. MPC5744P feature summary (continued)FeatureDetailsClockoutYesFaul t Control and Collection Unit (FCCU)YesCross Triggering Unit (CTU)2 moduleseTimer3 modules with 6 channelsFlexPWM2 modules with 4 x (2+1) channelsAnalog-to-digital converter (ADC)4 modules with 12-bit ADC, each with 16 channels (25external channels including shared channels plus internalchannels)Sine-wave generator (SGEN)32 pointSPI4 modulesAs many as 8 chip selectsCRC UnitYesSENT2 modules with 2 channelsInterprocessor serial link interface (SIPI)YesJunction temperature sensorYes (replicated module)Digital I/Os 16 Peripheral register protectionYesEthernetYesError Injection Module (EIM)YesSupplyDevice Power V with external ballast V with external V low drop-out (LDO)

4 RegulatorADC Analog Reference V to VClockingPhase Lock Loop (PLL)1 x PLL and 1 coupled FMPLLI nternal RC Oscillator16 MHzExternal Crystal Oscillator8 MHz to 40 MHzLow power modesHALT and STOPYesDebugNexusLevel 3+, MDO and Aurora interfacePackageLQFP144 pins, mm pitch, 20 mm x 20 mm outlineMAPBGA257 MAPBGA, mm pitch, 14 mm x 14 mm outlineTemperatureTemperature range (junction)-40 C to +150 C, option for 165 CAmbient temperature range (LQFP)-40 C to +125 C, 135 C option (with 165 C junction option)Ambient temperature range (BGA)-40 C to +125 C, 135 C option (with 165 C junction option)IntroductionMPC5744P data Sheet , Rev. , 11/20174 NXP SemiconductorsTable 2. Flash memory and SRAM sizes of MPC5744P , MPC5743P, MPC5742P, andMPC5741 PPart numberFlash MB384 MB256 MB192 MB128 DiagramThe following figure is a top-level diagram that shows the functional organization of 1.

5 System Block DiagramIntroductionMPC5744P data Sheet , Rev. , 11/2017 NXP pinouts and ballmapThe following figures show the LQFP pinout and the BGA 2. 144 LQFP pinout2 PinoutsMPC5744P data Sheet , Rev. , 11/20176 NXP SemiconductorsFigure 3. 257 MAPBGA ballmapPinoutsMPC5744P data Sheet , Rev. , 11/2017 NXP descriptionsThe following sections provide signal descriptions and related information about thefunctionality and configuration of the device. Note that this section is under startup and reset statesThe following table provides startup state and reset state information for device startup state and subsequent states of the following pins/balls cannot be configuredby the user: JCOMP TMS TCK XTAL/EXTAL FCCU_F[0] and FCCU_F[1] EXT_POR_B RESET_BThe user can configure the state after reset of the following pins/balls by programmingthe applicable MSCRs/IMCRs: GPIOs Analog inputs TDI TDO NMI_B FAB ABS[0] ABS[2]Table 3.

6 Pin/ball startup and reset statesPin/ballStartup state1, 2 State during resetState after reset144 LQFP257 MAPBGAGPIOshi-zhi-zhi-zNote3 Note3 Analog inputs4hi-zhi-zhi-zNote3 Note3 JCOMP (TRST)hi-zinput, weak pull-downinput, weak pull-downNote5 Note5 TDIhi-zinput, weak pull-upinput, weak pull-upNote5 Note5 TDOhi-zoutput, hi-zoutput, hi-zNote5 Note5 TMS6hi-zinput, weak pull-upinput, weak pull-upNote5 Note5 Table continues on the next data Sheet , Rev. , 11/20178 NXP SemiconductorsTable 3. Pin/ball startup and reset states (continued)Pin/ballStartup state1, 2 State during resetState after reset144 LQFP257 MAPBGATCK6hi-zinput, weak pull-upinput, weak pull-upNote5 Note5 XTAL/EXTALhi-zhi-zhi-zNote5 Note5 FCCU_F[0]6hi-zinput, hi-zoutput/input, hi-z38R2 FCCU_F[1]6hi-zinput, hi-zoutput/input, hi-z141C4 EXT_POR_Bhi-zinput, weak pull-downinput, weak pull-downNote5 Note5 RESET_Bhi-zinput, weak pull-downinput, weak pull-downNote5 Note5 NMI_Bhi-zinput, weak pull-upinput,weak pull-upNote5 Note5 FABhi-zinput, weak pull-downinput, weak pull-downNote5 Note5 ABS[2]hi-zinput, weak pull-downinput, weak pull-downNote5 Note5 ABS[0]

7 Hi-zinput, weak pull-downinput, weak state is exited when the core and high-voltage supplies reach minimum marked high impedance for POR will be in either high-impedance or weak low drive state when VDD_LV_CORE isoff and HV_VDD_IO is below Generic all non-supply or reference pins on the device are explicitly defined in this System pin/ball is dedicated to and directly connected to a peripheral module supply and reference voltage pins/ballsTable 4. Power supply and reference voltage pins/ballsSupplyPackageSymbolTypeDescrip tion144 LQFP257 MAPBGAVDD_LV_CORP owerLow voltage power Supply18397093131135F6F7F8F9F10F11F12G6G 12H6H12J6J12K6K12 Table continues on the next data Sheet , Rev. , 11/2017 NXP Semiconductors9 Table 4. Power supply and reference voltage pins/balls (continued)SupplyPackageSymbolTypeDescri ption144 LQFP257 MAPBGAL6L12M6M7M8M9M10M11M12 VSS_LV_CORG roundLow voltage ground.

8 PLL Ground is also connected to lowvoltage ground for core logic on 144 LQFP (pin 35).173540719496132137B1G7G8G9G10G11H7H8 H9H10H11J7J8J9J10J11K7K8K9K10K11L7L8L9L1 0L11 VDD_LV_PLLP owerPLL low voltage Supply36P4 VSS_LV_PLLG roundPLL low voltage Ground35N4 Table continues on the next data Sheet , Rev. , 11/201710 NXP SemiconductorsTable 4. Power supply and reference voltage pins/balls (continued)SupplyPackageSymbolTypeDescri ption144 LQFP257 MAPBGAVDD_HV_IOPowerHigh voltage Power Supply for I/O6217291126A9B2B16D8D14G2M2T2T16U14 VSS_HV_IOGroundHigh voltage Ground Supply for I/O72290127A1A2A16A17B1B9B17C3C15D9H2N2R 3R15T1T17U1U2U16U17 VDD_HV_PMUVDD_HV_PMU_AUXP owerPMU high voltage Supply72U14 VDD_HV_OSCP owerPower Supply for the oscillator27M1 VSS_HV_OSCG roundGround Supply for the oscillator28P1 VDD_HV_FLAP owerPower Supply and decoupling pin for flash memory97H16 VDD_HV_ADVP owerHigh voltage Supply for ADC, TSENS, SGEN ( V)58T10 VSS_HV_ADVG roundHigh voltage Ground for ADC59U9 Table continues on the next data Sheet , Rev.

9 , 11/2017 NXP Semiconductors11 Table 4. Power supply and reference voltage pins/balls (continued)SupplyPackageSymbolTypeDescri ption144 LQFP257 MAPBGAVDD_HV_ADRE0 SupplyHigh voltage Supply for digital portion of ADC padsVoltage reference of ADC/TSENSHigh voltage Supply for ADC0 pads and shared pads forADC0 voltage Ground for digital portion of ADC padsVoltage reference Ground of ADC/TSENSHigh voltage Ground for ADC0 pads and shared pads forADC0 voltage Supply for digital portion of ADC padsVoltage reference of ADC/TSENSHigh voltage Supply for ADC1 pads, shared pads for ADC1/3,and shared pads for ADC2 voltage Ground for digital portion of ADC padsVoltage reference Ground of ADC/TSENSHigh voltage Ground for ADC1 pads, shared pads forADC1/3, and shared pads for ADC2 PLL low voltage Supply N16 VSS_LV_LFASTG roundLFAST PLL low voltage Ground N17 VDD_LV_NEXUSS upplyAurora LVDS Supply J16 VSS_LV_NEXUSG roundAurora LVDS Ground pins/ballsThe following table contains information about system pin functions for the 5.

10 System pins/ballsSymbolTypeDescription144 LQFP257 MAPBGANMI_BInputNon-maskable Interrupt1E4 XTALO utputOutput of the oscillator amplifier circuit29N1 EXTALI nputCrystal oscillator input/external clock input30R1 RESET_BInputFunctional Reset31P2 EXT_POR_BInputExternal Power On Reset130D6 VPP_TEST1 InputSoC Test Mode107D15 JCOMPI nputJTAGC, JTAG Compliance Enable123A6 TCKI nputJTAGC, Test Clock Input88H17 TMSI nputJTAGC, Test Mode Select87H15 TDOO utputJTAGC, Test data Out89G14 Table continues on the next data Sheet , Rev. , 11/201712 NXP SemiconductorsTable 5. System pins/balls (continued)SymbolTypeDescription144 LQFP257 MAPBGATDII nputJTAGC, Test data Input86J17 MDO[0]OutputNEXUS, Message data out pins; reflects the state ofthe internal power on reset signal until RESET isnegated9G1 MDO[3:1]OutputNEXUS, Message data out pins4,5,8E1, F1, E2 EVTOO utputNEXUS, Event Out Pin24K2 EVTII nputNEXUS, Event In Pin25L2 MCKOO utputNEXUS, Message clock out pin19J4 MSEO[1:0]OutputNEXUS, Message Start/End out pin20, 23J3, K3 RDY_BOutputNEXUS, Read/Write Transfer completed J216K1 BCTRLO utputBase control signal of external npn ballast69R13J[11], J[10]--FSL Factory Test2 L17, must be connected to not connect on the pins/ballsThe following tables contain information on LVDS pin functions for the 6.