PCA9555 - NXP

1 PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt Rev. 10 8 November 2017 Product data sheet 1. General description The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O. configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers . The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register.

2 The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I2C-bus address compatible with the PCF8575, software changes are required due to the enhancements, and are discussed in Application Note AN469. The PCA9555 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight devices to share the same I2C-bus/SMBus. The fixed I2C-bus address of the PCA9555 is the same as the PCA9554, allowing up to eight of these devices in any combination to share the same I2C-bus/SMBus. 2. Features and benefits Operating power supply voltage range of V to V.

3 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101. NXP Semiconductors PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA. Five packages offered: SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24. 3. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9555D PCA9555D SO24 plastic small outline package; 24 leads; SOT137-1. body width mm PCA9555DB PCA9555 SSOP24 plastic shrink small outline package; 24 leads; SOT340-1. bodywidth mm PCA9555PW PCA9555 TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1. body width mm PCA9555BS 9555 HVQFN24 plastic thermal enhanced very thin quad flat package; SOT616-1.

4 No leads; 24 terminals; body 4 4 mm PCA9555HF P55H HWQFN24 plastic thermal enhanced very very thin quad flat SOT994-1. package; no leads; 24 terminals; body 4 4 mm Ordering options Table 2. Ordering options Type number Orderable Package Packing method Minimum Temperature part number order quantity PCA9555D PCA9555D,112 SO24 STANDARD MARKING * IC'S 1200 Tamb = 40 C to +85 C. TUBE - DSC BULK PACK. PCA9555D,118 SO24 REEL 13" Q1/T1 *STANDARD 1000. MARK SMD. PCA9555DB PCA9555DB,112 SSOP24 STANDARD MARKING * IC'S 826 Tamb = 40 C to +85 C. TUBE - DSC BULK PACK. PCA9555DB,118 SSOP24 REEL 13" Q1/T1 *STANDARD 1000. MARK SMD. PCA9555PW PCA9555PW,112 TSSOP24 STANDARD MARKING * IC'S 1575 Tamb = 40 C to +85 C. TUBE - DSC BULK PACK. PCA9555PW,118 TSSOP24 REEL 13" Q1/T1 *STANDARD 2500. MARK SMD. PCA9555BS PCA9555BS,118 HVQFN24 REEL 13" Q1/T1 *STANDARD 6000 Tamb = 40 C to +85 C. MARK SMD. PCA9555 BSHP HVQFN24 REEL 13" Q2/T3 *STANDARD 6000. MARK SMD. PCA9555HF PCA9555HF,118 HWQFN24 REEL 13" Q1/T1 *STANDARD 6000 Tamb = 40 C to +85 C.

5 MARK SMD. PCA9555 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2017. All rights reserved. Product data sheet Rev. 10 8 November 2017 2 of 34. NXP Semiconductors PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt 4. Block diagram PCA9555 . IO1_0. IO1_1. 8-bit IO1_2. A0. INPUT/ IO1_3. A1 OUTPUT. A2 IO1_4. PORTS. write pulse IO1_5. IO1_6. read pulse IO1_7. I2C-BUS/SMBus CONTROL. SCL IO0_0. INPUT. FILTER IO0_1. SDA. 8-bit IO0_2. INPUT/ IO0_3. OUTPUT. IO0_4. PORTS. write pulse IO0_5. IO0_6. read pulse VDD POWER-ON IO0_7. RESET. VSS VDD. LP filter INT. 002aac702. Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9555 . 5. Pinning information Pinning INT 1 24 VDD. A1 2 23 SDA. A2 3 22 SCL. IO0_0 4 21 A0. IO0_1 5 20 IO1_7. IO0_2 6 19 IO1_6. PCA9555D. IO0_3 7 18 IO1_5. IO0_4 8 17 IO1_4. IO0_5 9 16 IO1_3. IO0_6 10 15 IO1_2. IO0_7 11 14 IO1_1. VSS 12 13 IO1_0. 002aac698. Fig 2. Pin configuration for SO24.

6 PCA9555 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2017. All rights reserved. Product data sheet Rev. 10 8 November 2017 3 of 34. NXP Semiconductors PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt INT 1 24 VDD INT 1 24 VDD. A1 2 23 SDA A1 2 23 SDA. A2 3 22 SCL A2 3 22 SCL. IO0_0 4 21 A0 IO0_0 4 21 A0. IO0_1 5 20 IO1_7 IO0_1 5 20 IO1_7. IO0_2 6 19 IO1_6 IO0_2 6 19 IO1_6. PCA9555DB PCA9555PW. IO0_3 7 18 IO1_5 IO0_3 7 18 IO1_5. IO0_4 8 17 IO1_4 IO0_4 8 17 IO1_4. IO0_5 9 16 IO1_3 IO0_5 9 16 IO1_3. IO0_6 10 15 IO1_2 IO0_6 10 15 IO1_2. IO0_7 11 14 IO1_1 IO0_7 11 14 IO1_1. VSS 12 13 IO1_0 VSS 12 13 IO1_0. 002aac699 002aac700. Fig 3. Pin configuration for SSOP24 Fig 4. Pin configuration for TSSOP24. 20 SDA. 19 SCL. 21 VDD. 20 SDA. 22 INT. 19 SCL. 21 VDD. terminal 1. 24 A2. 23 A1. 22 INT. terminal 1. 24 A2. 23 A1. index area index area IO0_0 1 18 A0 IO0_0 1 18 A0. IO0_1 2 17 IO1_7 IO0_1 2 17 IO1_7. IO0_2 3 16 IO1_6 IO0_2 3 16 IO1_6.

7 PCA9555BS PCA9555HF. IO0_3 4 15 IO1_5 IO0_3 4 15 IO1_5. IO0_4 5 14 IO1_4 IO0_4 5 14 IO1_4. IO0_5 6 13 IO1_3 IO0_5 6 13 IO1_3. IO1_0 10. IO1_1 11. IO1_2 12. 7. 8. 9. IO1_0 10. IO1_1 11. IO1_2 12. 7. 8. 9. IO0_6. IO0_7. VSS. IO0_6. IO0_7. VSS. 002aac701 002aac881. Transparent top view Transparent top view Fig 5. Pin configuration for HVQFN24 Fig 6. Pin configuration for HWQFN24. PCA9555 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2017. All rights reserved. Product data sheet Rev. 10 8 November 2017 4 of 34. NXP Semiconductors PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt Pin description Table 3. Pin description Symbol Pin Description SO24, SSOP24, HVQFN24, TSSOP24 HWQFN24. INT 1 22 interrupt output (open-drain). A1 2 23 address input 1. A2 3 24 address input 2. IO0_0 4 1 port 0 input/output IO0_1 5 2. IO0_2 6 3. IO0_3 7 4. IO0_4 8 5. IO0_5 9 6. IO0_6 10 7. IO0_7 11 8. VSS 12 9[1] supply ground IO1_0 13 10 port 1 input/output IO1_1 14 11.

8 IO1_2 15 12. IO1_3 16 13. IO1_4 17 14. IO1_5 18 15. IO1_6 19 16. IO1_7 20 17. A0 21 18 address input 0. SCL 22 19 serial clock line SDA 23 20 serial data line VDD 24 21 supply voltage [1] HVQFN and HWQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9555 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2017. All rights reserved. Product data sheet Rev. 10 8 November 2017 5 of 34. NXP Semiconductors PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt 6. Functional description Refer to Figure 1 Block diagram of PCA9555 .

9 Device address slave address 0 1 0 0 A2 A1 A0 R/W. fixed programmable 002aac219. Fig 7. PCA9555 device address registers Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Table 4. Command byte Command Register 0 Input port 0. 1 Input port 1. 2 Output port 0. 3 Output port 1. 4 Polarity Inversion port 0. 5 Polarity Inversion port 1. 6 Configuration port 0. 7 Configuration port 1. PCA9555 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2017. All rights reserved. Product data sheet Rev. 10 8 November 2017 6 of 34. NXP Semiconductors PCA9555 . 16-bit I2C-bus and SMBus I/O port with interrupt registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3.

10 Writes to this register have no effect. The default value X' is determined by the externally applied logic level. Table 5. Input port 0 Register Bit 7 6 5 4 3 2 1 0. Symbol Default X X X X X X X X. Table 6. Input port 1 register Bit 7 6 5 4 3 2 1 0. Symbol Default X X X X X X X X. registers 2 and 3: Output port registers This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 7. Output port 0 register Bit 7 6 5 4 3 2 1 0. Symbol Default 1 1 1 1 1 1 1 1. Table 8. Output port 1 register Bit 7 6 5 4 3 2 1 0. Symbol Default 1 1 1 1 1 1 1 1. registers 4 and 5: Polarity Inversion registers This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with 1'), the Input port data polarity is inverted.