PUSB3FR4 - Nexperia

1 PUSB3FR4 ESD protection for ultra high-speed interfaces12 July 2018 Product data sheet1. General descriptionThe device is designed to protect high-speed interfaces such as SuperSpeed USB at 10 Gbps,High-Definition Multimedia Interface (HDMI), DisplayPort, external Serial Advanced TechnologyAttachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces against ElectroStaticDischarge (ESD).The device includes four high-level ESD protection diode structures. They protect sensitivetransmitters and receivers for ultra high-speed signal lines. The device is encapsulated in aleadless small DFN2510A-10 (SOT1176-1) plastic signal lines are protected by a special diode configuration offering ultra low line capacitanceof only pF. These diodes utilize a snap-back structure in order to provide protection todownstream components from ESD voltages up to 15 kV contact exceeding IEC 61000-4-2,level Features and benefits System-level ESD protection for USB and SuperSpeed USB at 10 Gbps, HDMI,DisplayPort, eSATA and LVDS Line capacitance of only pF for each channel Outstanding system protection: extremely deep snap-back combined with dynamic resistanceof only All signal lines with integrated rail-to-rail clamping diodes for downstream ESD protection of 15kV exceeding IEC 61000-4-2, level 4 Matched mm trace spacing Signal lines with pF matching capacitance between signal pairs Design-friendly pass-through signal routing3.

2 ApplicationsThe device is designed for high-speed receiver and transmitter port protection: Smartphones, tablet computers, Mobile Internet Devices (MID) and portable devices TVs and monitors DVD recorders and players Notebooks, main board graphic cards and ports Set-top boxes and game consolesNexperiaPUSB3FR4 ESD protection for ultra high-speed interfaces4. Pinning informationTable 1. Pinning informationPinSymbolDescriptionSimplifie d outlineGraphic symbol1CH1channel 1 ESD protection2CH2channel 2 ESD protection3 GNDground4CH3channel 3 ESD protection5CH4channel 4 ESD connectedTransparent top view10987612345 DFN2510A-10 (SOT1176-1)CH1CH2CH3CH4 GND=aaa-0163295. Ordering informationTable 2. Ordering informationPackageType numberNameDescriptionVersionPUSB3FR4 DFN2510A-10plastic, leadless extremely thin small outline package; 10terminals; mm pitch; mm x 1 mm x mm bodySOT1176-16.

3 MarkingTable 3. Marking codesType numberMarking codePUSB3FR4 FRPUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20182 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfaces7. Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).SymbolParameterConditionsMinMaxUn itVIinput peak pulse currenttp = 8/20 s-7 AIEC 61000-4-2, level 4; contact discharge[1]-1515kVVESD electrostatic dischargevoltageIEC 61000-4-2, level 4; air discharge[1]-1515kVTstgstorage temperature-55125 CTambambient temperature-4085 C[1] All pins to CharacteristicsTable 5. CharacteristicsSymbolParameterConditions MinTypMaxUnitVBRbreakdown voltageII = 1 mA; Tamb = 25 leakagecurrentper channel; VI = V; Tamb = 25 C-1100nAVFforward voltageII = 1 mA; Tamb = 25 capacitancef = 1 MHz; VI = V; Tamb = 25 C[1] Clineline capacitancedifferencef = 1 MHz; VI = V; Tamb = 25 C[1] ; positive transient; Tamb = 25 C[2] rdyndynamic resistanceTLP; negative transient; ; Tamb = 25 C[2] Vsbcksnapback voltageII = 1 A; TLP 10/100 ns; Tamb = 25 = 5 A; positive transient;Tamb = 25 C[3]-3-VVCL clamping voltageIPP = -5 A; negative transient;Tamb = 25 C[3]--3-V[1] The parameter is guaranteed by design.

4 [2] 100 ns Transmission Line Pulse (TLP), 50 , pulser at 80 ns.[3] According to IEC 61000-4-5 (8/20 s current waveform). PUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20183 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfacesaaa-016314-3-11S21dd(dB)-5f (Hz)1061010109107108differential modeFig. loss; typical valuesVI (V) 2 and 4pin 1 and 5 Fig. capacitance as a function of inputvoltage; typical valuesaaa-016316-60-40-80-200 Sdd21(dB)-100f (Hz)1081010109 Sdd21 normalized to 100 ;differential pairs CH1/CH2 versus CH3/CH4 Fig. differential NEXT crosstalk; typicalvaluest (ns) ( )10595858090100110(2)(1)tr = 200 ps; differential pair CH1 + CH2(1) Device on reference board(2) Reference board without Device Under Test(DUT)Fig.

5 Time Domain Reflectometer (TDR)plot; typical valuesPUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20184 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfacesaaa-016318 Data rate: 10 Gbit/sVertical scale: 175 mV/divHorizontal scale: 20 ps/divFig. eye diagram, PCB with deviceaaa-016319 Data rate: 10 Gbit/sVertical scale: 175 mV/divHorizontal scale: 20 ps/divFig. eye diagram, PCB without devicePUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20185 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfacesaaa-016320 Test frequency: MHzDifferential swing voltage: 812 mVHorizontal scale: 34 ps/divFig.

6 TP1 eye diagram, PCB with deviceaaa-016321 Test frequency: MHzDifferential swing voltage: 812 mVHorizontal scale: 34 ps/divFig. TP1 eye diagram, PCB without devicePUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20186 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfacesVCL (V)0251552010aaa-01632225 IPP(A)05101520tp = 100 ns; Transmission Line Pulse (TLP);tr = 1 nsFig. resistance with positive clamping;typical valuesVCL (V)-250-10-20-5-15aaa-0163230 IPP(A)-25-20-15-10-5tp = 100 ns; Transmission Line Pulse (TLP);tr = 1 nsFig. resistance with negative clamping;typical valuesVCL (V)070103050402060aaa-01632470 IPP(A)0102030405060tp = 5 ns; Transmission Line Pulse (TLP);tr = 600 psFig.

7 11. Dynamic resistance with positive clamping;typical valuesVCL (V)-700-60-40-20-30-50-10aaa-0163250 IPP(A)-70-60-50-40-30-20-10tp = 5 ns; Transmission Line Pulse (TLP);tr = 600 psFig. resistance with negative clamping;typical valuesPUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20187 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfacesVCL (V)0108462aaa-016326462810 IPP(A)0 IEC 61000-4-5; tp = 8/20 s; positive pulseFig. resistance with positive clamping;typical valuesVCL (V)-80-2-6-4aaa-016327-4-6-20 IPP(A)-8 IEC 61000-4-5; tp = 8/20 s; negative pulseFig. resistance with negative clamping;typical valuesPUSB3FR4 All information provided in this document is subject to legal disclaimers.

8 Nexperia 2018. All rights reservedProduct data sheet12 July 20188 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfaces9. Application informationThe device is designed to provide high-level ESD protection for high-speed serial data buses suchas HDMI, DisplayPort, eSATA and LVDS data : When designing the PCB, give careful consideration to impedance matching andsignal coupling. Do not connect the signal lines to unlimited current sources like, forexample, a diagram: protection of USB Type-C connector interface using PUSB3FR4 Dynamic resistanceThe device uses an advanced clamping structure showing a negative dynamic snap-back behavior strongly reduces the clamping voltage to the system behind the ESDprotection during an ESD event.

9 Do not connect unlimited DC current sources to the data lines toavoid keeping the ESD protection device in snap-back state after exceeding breakdown voltage(due to an ESD pulse for instance). PUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 20189 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfaces10. Package outline12-05-23 Dimensions in outline DFN2510A-10 (SOT1176-1) PUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 201810 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfaces11. SolderingSOT1176-1 Remark:Stencil of 75 m is stencil of 75 m gives an aspect ratio of a stencil of 100 m one will obtain an aspect ratio of information for reflow soldering of DFN2510A-10 packagesolder land plus solder pasteoccupied areasolder landsolder paste depositsolder in footprint patternRefer to the package outline drawing for actual layoutsot1176-1_frFig.

10 Soldering footprint for DFN2510A-10 (SOT1176-1) PUSB3FR4 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reservedProduct data sheet12 July 201811 / 15 NexperiaPUSB3FR4 ESD protection for ultra high-speed interfaces12. Revision historyTable 6. Revision historyData sheet IDRelease dateData sheet statusChange noticeSupersedesPUSB3FR4 data sheet- PUSB3FR4 : The format of this data sheet has been redesigned to comply with the identity guidelines ofNexperia. Legal texts have been adapted to the new company name where appropriate. Conditions clarified to reflect the used standard Figures 9 to 12 were updatedPUSB3FR4 data sheet-- PUSB3FR4 All information provided in this document is subject to legal disclaimers.