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Quad 2-input NAND gate - Nexperia

74HC00; 74 HCT00 Quad 2-input NAND gateRev. 9 22 October 2021 Product data sheet1. General descriptionThe 74HC00; 74 HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enablesthe use of current limiting resistors to interface inputs to voltages in excess of Features and benefits Wide supply voltage range from to V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC00: CMOS level For 74 HCT00: TTL level Complies with JEDEC standards: JESD8C ( V to V) JESD7A ( V to V) ESD protection.

Quad 2-input NAND gate Rev. 9 — 22 October 2021 Product data sheet 1. General description The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in …

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Transcription of Quad 2-input NAND gate - Nexperia

1 74HC00; 74 HCT00 Quad 2-input NAND gateRev. 9 22 October 2021 Product data sheet1. General descriptionThe 74HC00; 74 HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enablesthe use of current limiting resistors to interface inputs to voltages in excess of Features and benefits Wide supply voltage range from to V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC00: CMOS level For 74 HCT00: TTL level Complies with JEDEC standards: JESD8C ( V to V) JESD7A ( V to V) ESD protection.

2 HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C3. Ordering informationTable 1. Ordering informationPackageType numberTemperature rangeNameDescriptionVersion74HC00D74 HCT00D-40 C to +125 CSO14plastic small outline package; 14 leads;body width mmSOT108-174HC00PW74 HCT00PW-40 C to +125 CTSSOP14plastic thin shrink small outline package; 14 leads;body width mmSOT402-174HC00BQ74 HCT00BQ-40 C to +125 CDHVQFN14plastic dual in-line compatible thermal enhancedvery thin quad flat package; no leads; 14 terminals;body 3 mmSOT762-1 Nexperia74HC00; 74 HCT00 Quad 2-input NAND gate4.

3 Functional diagrammna2121A1Y1B1232A2Y2B4563A3Y3B910 84A4Y4B121311 Fig. symbolmna246312&645&8910&111213&Fig. logic symbolmna211 ABYFig. diagram (one gate)5. Pinning Pinning74HC00 74 HCT001 AVCC1B4B1Y4A2A4Y2B3B2Y3 AGND3Y001aal3231234567810912111413 Fig. configuration SOT108-1 (SO14) andSOT402-1 (TSSOP14)001aal32474HC00 74 HCT00 GND(1)Transparent top view2Y3A2B3B2A4Y1Y4A1B4 BGND3Y1 AVCC6951041131221378114terminal 1 index area(1) This is not a ground pin. There is no electrical ormechanical requirement to solder the pad. In casesoldered, the solder land should remain floating orconnected to configuration SOT762-1 (DHVQFN14) Pin descriptionTable 2.

4 Pin descriptionSymbolPinDescription1A, 2A, 3A, 4A1, 4, 9, 12data input1B, 2B, 3B, 4B2, 5, 10, 13data input1Y, 2Y, 3Y, 4Y3, 6, 8, 11data outputGND7ground (0 V)VCC14supply voltage74HC_HCT00 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 9 22 October 20212 / 12 Nexperia74HC00; 74 HCT00 Quad 2-input NAND gate6. Functional descriptionTable 3. Function tableH = HIGH voltage level; L = LOW voltage level; X = don t Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

5 Voltages are referenced to GND (ground = 0 V).SymbolParameterConditionsMinMaxUnitVC Csupply +7 VIIK input clamping currentVI < V or VI > VCC + V[1]- 20mAIOK output clamping currentVO < V or VO > VCC + V[1]- 20mAIOoutput V < VO < VCC + V- 25mAICC supply current-50mAIGND ground current-50-mATstgstorage temperature-65+150 CPtottotal power dissipation[2]-500mW[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For SOT108-1 (SO14) package: Ptot derates linearly with mW/K above 100 SOT402-1 (TSSOP14) package: Ptot derates linearly with mW/K above 81 SOT762-1 (DHVQFN14) package: Ptot derates linearly with mW/K above 98 Recommended operating conditionsTable 5.

6 Recommended operating conditionsVoltages are referenced to GND (ground = 0 V)74HC0074 HCT00 SymbolParameterConditionsMinTypMaxMinTyp MaxUnitVCCsupply voltage0-VCC0-VCCVVO output voltage0-VCC0-VCCVT ambambient temperature-40+25+125-40+25+125 CVCC = V--625---ns/VVCC = t/ Vinput transition rise and fall rateVCC = V--83---ns/V74HC_HCT00 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 9 22 October 20213 / 12 Nexperia74HC00; 74 HCT00 Quad 2-input NAND gate9. Static characteristicsTable 6.

7 Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).25 C-40 C to+85 C-40 C to+125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnit74HC00 VCC = = voltageVCC = = = voltageVCC = = VIH or VILIO = -20 A; VCC = = -20 A; VCC = = -20 A; VCC = = mA; VCC = voltageIO = mA; VCC = = VIH or VILIO = 20 A; VCC = = 20 A; VCC = = 20 A; VCC = = mA; VCC = voltageIO = mA; VCC = leakagecurrentVI = VCC or GND; VCC = V---- 1- 1 AICC supply currentVI = VCC or GND; IO = 0 A;VCC = V----20-40 voltageVCC = V to voltageVCC = V to = VIH or VIL.

8 VCC = VIO = -20 voltageIO = = VIH or VIL; VCC = VIO = 20 voltageIO = 4 information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 9 22 October 20214 / 12 Nexperia74HC00; 74 HCT00 Quad 2-input NAND gate25 C-40 C to+85 C-40 C to+125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnitIIinput leakagecurrentVI = VCC or GND; VCC = V---- 1- 1 AICC supply currentVI = VCC or GND; IO = 0 A;VCC = V----20-40 A ICCadditionalsupply currentper input pin;VI = VCC - V; IO = 0 A;other inputs at VCC or GND;VCC = V to V-150--675-735 Dynamic characteristicsTable 7.

9 Dynamic characteristicsGND = 0 V; CL = 50 pF; for test circuit see Fig. C-40 C to+85 C-40 C to+125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnit74HC00nA, nB to nY; see Fig. 6[1]VCC = V-25--115-135nsVCC = V-9--23-27nsVCC = V; CL = 15 pF-7-----nstpdpropagation delayVCC = V-7--20-23nssee Fig. 6[2]VCC = V-19--95-110nsVCC = V-7--19-22nstttransition timeVCC = V-6--16-19nsCPDpower dissipationcapacitanceper package;VI = GND to VCC[3]-22-----pF74 HCT00nA, nB to nY; see Fig. 6[1]VCC = V-12--24-29nstpdpropagation delayVCC = V; CL = 15 pF-10-----nstttransition timeVCC = V; see Fig.

10 6[2]----29-22nsCPDpower dissipationcapacitanceper package;VI = GND to VCC - V[3]-22-----pF[1]tpd is the same as tPHL and tPLH.[2]tt is the same as tTHL and tTLH.[3]CPD is used to determine the dynamic power dissipation (PD in W):PD = CPD VCC 2 fi N + (CL VCC 2 fo) where:fi = input frequency in MHz; fo = output frequency in MHz;CL = output load capacitance in pF;VCC = supply voltage in V;N = number of inputs switching; (CL VCC 2 fo) = sum of information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev.